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Getting reacquainted with NAND flash

Posted: 01 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Jim Cooke? Micron? spotlight? handset memory? storage?

For many consumer A/V products, NAND flash memory is a better storage choice than HDD, especially in low-capacity applications (4Gbytes or less). As the quest continues for lower-power, lighter, more robust products, NAND is proving to be very attractive.

The NAND flash array is grouped into a series of 128Kbyte blocks, which are the smallest erasable entity in a NAND device. Erasing a block sets all bits to "1" (all bytes to FFh). Programming is necessary to change erased bits from a 1 to a 0. The smallest entity that can be programmed is a byte. Some NOR flash memory can perform read-while-write operations. Although NAND can't perform read and write simultaneously, it can accomplish this at a system level using shadowing, a method which has been used on PCs for years by loading the BIOS from the slower ROM into the higher-speed RAM.

NAND efficiencies are due to the lack of metal contacts in the NAND string. NAND flash cell size is smaller than NOR, 4F? vs. 10F?, since NOR cells require a separate metal contact for each cell.

Due to the decrease in die area resulting from the small cell size, NAND provides the larger capacities required for today's low-cost consumer market. NAND flash is used in almost all removable memory cards. NAND's multiplexed interface provides a similar pin-out for all recent devices and densities. This pin-out lets designers use small densities and migrate to larger densities without any hardware changes to the PCB.

NAND basic operation
The 2Gbit NAND device is organized as 2,048 blocks, with 64 pages per block. Each page has 2,112bytes total, comprised of a 2,048byte data area and a 64byte spare area. The spare area is typically used for ECC, wear-leveling information and other software overhead functions, although it's physically no different from the rest of the page. NAND devices are offered with either an 8bit or 16bit interface.

Host data is connected to the NAND memory through an 8bit- or 16bit-wide bidirectional data bus. In 16bit mode, commands and addresses use only the lower 8bits. The upper 8bits are only used during data-transfer cycles.

Erasing a block requires about 2ms. Once the data is loaded in the register, programming a page requires about 300μs. A page read requires approximately 25μs, in which the page is accessed from the array and loaded into the 16,896bit register. The register is then available for the user to clock out the data.

In addition to the I/O bus, the NAND interface is comprised of six major control signals:

  • Chip enable (CE#)!If CE# is not asserted, the NAND will remain in standby mode and not respond to control signals.

  • Write enable (WE#)!WE# is responsible for clocking data, address or commands into the NAND.

  • Read enable (RE#)!RE# will enable the output data buffers.

  • Command latch enable (CLE)!When CLE is high, commands are latched into the NAND command register on the rising edge of the WE# signal.

  • Address latch enable (ALE)!When ALE is high, addresses are latched into the NAND address register on the rising edge of the WE# signal.

  • Ready/busy (R/B#)!If the NAND device is busy, the R/B# signal will be asserted low. This signal is open drain and needs a pull-up resistor.

Connecting NAND
Selecting a processor or a controller with a built-in NAND interface has advantages. If this option isn't available, it's possible to design a glueless interface between the NAND and almost any processor. The main difference between NAND and NOR flash is the multiplexed address and data bus. This bus is used to specify commands, address or data.

The CLE signal specifies command cycles, while the ALE signal specifies address cycles. These two control signals can be used to select a command, address or data cycle. Connecting ALE to the processor's address bit five and CLE to the processor's address bit four enables the selection of either command, address or data simply by changing the address that the processor outputs. This allows CLE and ALE to be asserted automatically at the appropriate time.

To supply a command, the processor outputs the intended command on the data bus and output address 0010h. To supply any number of address cycles, the processor simply needs to output the intended NAND address sequence to processor address 0020h. Note that many processors can specify several timing parameters around the processor's write signal, which is critical for proper timing. Using this technique, you can access commands, address and data directly from the processor without any glue logic. In this case, ECC would have to be handled in the software.

Error correction
NAND requires ECC to ensure data integrity. NAND flash includes extra storage on each page. The extra storage is the spare area of 64bytes (16bytes per 512byte sector). This area can store the ECC code and other information like wear-leveling or logical-to-physical block-mapping. ECC can be performed in hardware or software, but hardware implementation provides an obvious performance advantage. During a programming operation, the ECC unit calculates the error-correcting code based on the data stored in the sector. The ECC code for the respective data area is then written on the respective spare area. When the data is read out, the ECC code is also read, and the reverse operation is applied to check if the data is correct.

The ECC algorithm can correct data errors. The number of errors that can be corrected depends on the correction strength of the algorithm used. Including ECC in hardware or software provides a robust system-level solution.

Software is needed to perform the NAND flash's block management. This software is responsible for wear-leveling or logical-to-physical mapping. The software may also provide the ECC code if the processor does not include ECC hardware.

Reading the status register after a program or erase operation is important, as it confirms successful completion of the operation. If the operation wasn't successful, the block should be marked bad and shouldn't be used. Previously programmed data should be moved out of the bad block into a new (good) block. Due mostly to their large die size, NAND devices can ship from the factory with some bad blocks. The software managing the device is responsible for mapping the bad blocks and replacing them with good blocks.

The bad-block marks should not be erased. The factory tests NAND over a wide range of temperatures and voltages. Some blocks marked as bad by the factory may be functional at certain temperatures or voltages but could fail in the future. If the bad-block information is erased, it can no longer be recovered.

- Jim Cooke
Principal Applications Engineer
Memory Products Group
Micron Technology Inc.




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