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Migration to 90nm faster than expected

Posted: 02 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:90nm? DFM? ASIC? Open-Silicon? 130nm?

With 90nm designs quickly moving into the mainstream, engineers face trade-offs in balancing design-for-manufacturing (DFM) guidelines against extracting the performance and die-shrink improvements the technology promises.

"Engineers have to put on their thinking caps and use their analytical abilities and experience," said Jay Jayaprakash, an ASIC design manager with Open-Silicon Inc., the design services company that organized the "90nm Summit" last August. "If we follow all the DFM rules, we can start out with a 90nm design and effectively buy a 130nm design, which brings us nothing."

Despite such challenges, said Naveed Sherwani, president and CEO of Open-Silicon, the transition to 90nm designs is proceeding more smoothly than the earlier move to 130nm design rules. Then, delays in certain EDA tools, particularly for physical design, and packaging issues related to low-k dielectrics in the interconnect layers, caused "several hiccups at 130," he said. Overall, the industrywide transition to 130nm was delayed by two years, he estimated.

With 90nm, "the transition has been very smooth and fast," Sherwani said.

"About one-third of design starts at the foundries are at 90nm, and that is rising rapidly," he said. "There is tons of capacity at 90nm at multiple fabs."

While a typical 130nm design requires 12 basic design steps, 90nm designs involve a 20-plus-step flow. Many designs, for example, involve multiple threshold voltages to cut down on leakage currents, requiring dynamic power analysis.

Leakage matters
Open-Silicon works closely with Taiwan-based Semiconductor Manufacturing Co., which offers two flavors of multiple-threshold transistors. One, called MTCMOS, can be switched on the fly under logic control. It offers higher-density routing signals and is optimized for a relatively small logic blocka 25,000-gate decode engine in a processor, for example. Another multiple-threshold voltage technology is called MultiVt CMOS, which are fixed higher-threshold-voltage transistors that can be placed anywhere in the design. While they reduce leakage by 30 percent, the MultiVt transistors are relatively slow.

DFM tools can help check the placement of these low-leakage transistors, providing "soft checks, which provide 'should have' or 'could have' guidelines instead of 'must haves.' But engineers have to keep aware and think intelligently" as they face DFM choices, he said.

One of the most difficult challenges is achieving uniform metal utilization, which, Jayaprakash said, "in my daily life experience is very hard to do and still get the timing slack right."

To prevent uneven chemical mechanical polishing, foundries like TSMC require that metal wires be distributed fairly evenly across the die. This requirement, if followed too strictly, can result in wire spreading, which kills the density improvements inherent within 90nm technologies. Similarly, foundries publish DFM guidelines, which in certain situations require multiple or mandatory redundant vias. Again, engineers must figure out how to follow the via and metal-spreading requirementsaimed largely at improving yieldswithout going too far and bloating the die size.

Test is another critical area. In 90nm designs, Jayaprakash said, "bridging defects dominate," in which metal lines and other structures create bridges that short out the circuits.

Some test strategies result in test costs approaching $2 per chip, which is unacceptable in today's strict consumer pricing environment. "Test time is increasing, so what do we do?" he asked.

"We no longer have just stuck-at faults. Today, we have very big drivers with very thin wires, and delay faults are the issue," he said. What might test out as acceptable at a slow speed will not pass when the device is operated at 500MHz, and certain transistors must switch at 100ps.

Right test
That means design-for-test is becoming an integral part of the overall design strategy, rather than a stuck-at-fault test pattern that is tacked on separately. "As we go to finer geometries, there is a confluence of delay information, which helps create a test failure pattern," he said.

Ching-Cheng Chai, a design services marketing manager at TSMC, said the foundry has accepted 190 of the 90nm tape-outs thus far. While 90nm wafers accounted for about 16 percent of TSMC's capacity six months ago, that figure has grown to 24 percent today. The company's low-power (90LP) process, designed for low-standby-power applications, accounts for about half of its 90nm wafers, with the generic (90G) process and the faster "generic turbo" (90GT) process sharing the remaining half.

Additional EDA steps needed for 90nm designs. Major challenges include power, test, signal integrity and package co-design.

In 300mm-wafer-equivalents, TSMC processed 150,000 at 90nm design rules in Q4 2005. That increased sharply to 375,000 wafers in Q2 2006 as the company continues to fill out its 300mm Fab 14 wafer complex in Tainan.

One design engineer in the audience challenged TSMC, asking Chai why it has taken so long to see qualified IP cores at 90nm. Chai said IP providers have seen their own development costs increasing, leading customers to delay their commitments to purchase those IP cores. Nevertheless, he showed a chart heavily populated with IP vendors that support 90nm design rules now, including 13 mixed-signal IP vendors.

TSMC has been filling out its own 90nm technology licensing portfolio. Last week, TSMC and Silicon Storage Technology (SST) announced an agreement to port SST's split-gate flash technology to TSMC. The embedded flash uses a split-gate, source-side injection, poly-erase memory cell that is easily integrated with logic on MCUs and other ICs. Samples will be available next year.

Chai said TSMC is also working on diagonal X Architecture interconnects, embedded DRAM and electrical fuses to modify logic circuits.

By year's end, TSMC will make a linear shrink, offering 80nm technology, which, he said, will improve performance by 10 percent. An 80GC (general consumer) process will be offered, which reduces leakage sharply, Chai said.

- David Lammers
EE Times




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