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Displaytech moves to Synopsys synthesis tool for FLCOS microdisplays

Posted: 05 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Displaytech? Synopsys? synthesis tool? FLCOS backplane? FLCOS?

Displaytech Inc. has moved to the Synopsys' Design Compiler synthesis tool in meeting the design schedule of its next-generation ferroelectric liquid-crystal-on-silicon (FLCOS) backplane. The FLCOS backplane is for high-resolution, high-speed microprojection and holographic data storage systems. The new microdisplays deliver high-speed light switching to produce brilliant, real-life digital images, said the press release.

"We needed a new synthesis solution to deal with the challenging timing and power goals for our next-generation microdisplays and found Design Compiler to be a superior synthesis solution capable of addressing our design challenges," said Bruce Spenner, executive VP at Displaytech, in a statement.

Due to significant enhancements implemented last year, said Synopsys, the Design Compiler solution now incorporates topographical technology, using the company's advanced physical implementation technologies to drive accurate timing to allow for accurate prediction of post-layout timing, area and power during synthesis. Synopsys also said that its compiler can eliminate costly iterations between synthesis and layout and generate a better start point for physical implementation faster.

"We continue to innovate in synthesis to enable our customers to meet their most demanding design challenges while shortening their overall chip development schedules," said Antun Domic, senior VP and GM of Synopsys Implementation Group. "Customers like Displaytech depend on the performance and productivity that Design Compiler delivers to meet their critical time-to-market goals."




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