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ESL tool offers embedded software support in SystemC

Posted: 16 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Electronic system-level? ESL? Space Codesign? design tool? embedded software?

Electronic system-level (ESL) tools today aim primarily at hardware designers, but an upcoming SystemC architectural design tool expects to provide strong support for embedded-software development. That's the idea behind Space Codesign, a startup that Canadian university researchers are spinning out from the Polytechnic School of Montreal.

The researchers are preparing a tool set that lets users capture a complete high-level architecture using SystemC modules and run simulation with no notion of hardware and software. Users can then do HW/SW partitioning using a SystemC RTOS interface.

Next, with the help of an instruction-set simulator, users develop a cycle-accurate architectural model. Finally, they can generate the applications software and map the hardware to an FPGA.

With help and funding from Univalor, a partnership that helps commercialize research from several universities in Montreal, Space Codesign expects to incorporate next year and to have products ready for beta sites in early 2007.

Space Codesign's technology follows five years of research into ESL tools, said co-founder Guy Bois, a Montreal Polytechnic professor who believes the time has come for commercialization. "More and more people believe in ESL," Bois said, "and I think this is a good window."

While ESL products and companies abound, Space Codesign's embedded software support sets it apart, Bois said. Its tools will support commercial RTOSes and instruction-set simulators. A second distinction is drag-and-drop HW/SW partitioning. "We can move blocks from hardware to software and vice versa without any recoding, since everything is in SystemC," Bois said.

Software vs. hardware
One potential obstacle is that few software developers use SystemC today. "I believe one reason is the current lack of embedded software support in SystemC," Bois said. "Space Codesign proposes a solution to that problem. With Space Codesign, the software engineer can see the implication of implementing a task in software rather than in hardware."

Moreover, said Luc Filion, a Ph.D. student involved with Space Codesign research, the user interface makes SystemC largely transparent. "Our technology simplifies or hides SystemC complexity and provides an enjoyable environment for building software blocks," he said. "You can easily build a whole system environment and still be in SystemC without knowing it."

Tools model RTOS and instruction set simulator.

Space Codesign is providing an "architect's workbench," one of two "killer apps" for ESL, said Gary Smith, chief EDA analyst at Gartner Dataquest. "They are new engineers with new ideas, the kind who come up with breakthrough products," he said. "It will be fun to see what they come up with."

Space Codesign offers a four-step process involving a SystemC refinement methodology that uses software abstraction levels to facilitate HW/SW partitioning. The first two steps are contained in the Elix product. Elix lets users develop and validate their architectures, and do an initial partitioning.

"Elix has both timed and untimed behaviors but keeps everything at a very high level," said Filion. "You can create a very light model of your embedded system and have it simulated very quickly."

Filion noted that systems engineers can use Elix to model complete applications. Most companies already do this in C or C++, he said, but with Elix, "you have a whole framework for doing it very quickly."

With step one, users bring their code into SystemC modules. Elix connects modules using communications channels. Models can also be instantiated from a library. Functional validation is performed at this level, with no distinction between hardware and software.

With step two, users start mapping modules to hardware or software. An RTOS runs on the host workstation to facilitate software simulation. Users can move a block like a FIFO from hardware to software, in which case the equivalent behavioral code will be executed in the RTOS. Space Codesign currently supports the MicroC RTOS from Micrium and is working on Wind River's VxWorks, Bois said.

Elix supports the programmer's-view-with-timing (PVT) approach to transaction-level modelingi.e. there's a rough notion of timing, but it's not cycle-accurate. In addition to simulation and debugging, Elix provides a graphical performance analysis tool.

Step three comes with the Simtek product. It creates a cycle-accurate model of the architecture and provides simulation. At this stage, users replace software simulation with an instruction-set simulator (ISS). Space Codesign has an ISS model for the Xilinx MicroBlaze architecture.

Hardware implementation comes with step four and a product called Gen-X Pro, still under development. The initial release will take the architecture defined in Simtek and map it directly into a Xilinx FPGA, using Xilinx's embedded development kit. Gen-X Pro can thus be seen as a "front-end" to the development kit, Bois said.

Software implementation is simply a matter of removing the SystemC structure, Bois said. The RTOS is already there, so there's no need to generate one.

There is, however, no translation between Simtek and the RTL code that would be needed for ASIC design. FPGA design, said Bois, is Space Codesign's "first goal." But the same technology can eventually target ASICs, he said. Space Codesign is not, however, developing behavioral synthesis from SystemC to RTL.

Wrapped around Elix and Simtek is the Space Studio, which provides a graphical interface based on the Eclipse open-source standard. It lets users create and manipulate SystemC blocks, as well as pull blocks from component libraries.

Space Codesign expects to launch with four or five employees involved in the research project. There's no president or CEO yet. But the company attracted interest at the recent Design Automation Conference and is talking with potential customers. Next year, it appears, a software-centric approach to ESL will be put to the test.

- Richard Goering
EE Times




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