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ARM, Cadence expand joint reference methodology

Posted: 27 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:ARM? Cadence? ATPG? RTL? GDSII?

Cadence Design Systems Inc. is collaborating with ARM to expand their joint Encounter Reference Methodology with the addition true-time test ATPG, touted to provide capabilities to develop tests that detect small delay defects while concurrently managing power consumption during test.

"The addition of Encounter Test to the Reference Methodology provides a high-value capability for design teams," said Keith Clarke, vice president of technical marketing at ARM. "Efficient detection of small delay defects and management of power during test are both important elements in getting the best results during development of ARM processor-based SoC."

According to the press release, the reference methodology is proven to deliver a powerful, deterministic and rapid route from RTL to GDSII for ARM synthesizable processors. It increases productivity and reduces time-to-silicon with predictable performance, power and area results. Moreover, by providing accurate abstract models, the methodology enables licensees to deploy the ARM processor as a library component for SoC integration by end users.

Cadence Encounter Test is a key component of the Cadence Encounter digital IC design platform. It delivers the industry's 'most' advanced test solution from RTL to silicon. Key technologies include power-aware ATPG methods to reduce power during test, test data compression to lower cost of test, True-Time delay test to detect small delay defects and enable the highest quality of shippable silicon and Encounter Diagnostics to accelerate yield ramp.

"The inclusion of Encounter Test in the ARM and Cadence Encounter Reference Methodology is an important milestone not just for our partnership, but for the design community," said Sanjiv Taneja, vice president of R&D for Encounter Test at Cadence. "It provides the ARM user community with an important tool to ensure high quality electronic design. We look forward to future collaborations that advance the art of semiconductor test."




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