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Xilinx upgrades XtremeDSP to support Virtex-5 LX, LXT

Posted: 10 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? XtremeDSP? System Generator? AccelDSP? FPGA?

Xilinx Inc. has announced the immediate availability of version 8.2 of its XtremeDSP development tools. These tools consist of the System Generator for DSP and AccelDSP, which feature optimized DSP support for Xilinx Virtex-5 LX and LXT, said to be the industry's only 65nm FPGAs. The new version of the software tools enable DSP system designers and algorithm developers, who are unfamiliar with FPGAs, to design, simulate and verify DSP systems, Xilinx said, achieving up to 40 percent lower power, 10 percent higher DSP performance and significantly reduced area compared to previous generation Virtex-4 LX FPGAs.

"We are delivering on our promise to provide world-class DSP design tools and methodologies and this strategic focus is paying enormous dividends for our DSP customers," said Omid Tahernia, VP and general manager of the processing solutions group at Xilinx. "System Generator and AccelDSP development tools and the Virtex-5 FPGAs are key parts of our solutions strategy. Together they deliver the industry's highest DSP performance, lowest DSP power and area with development times that can be anywhere from five- to thirty-times shorter than traditional RTL design approaches. We're helping our customers gain a significant competitive advantage in their markets."

In addition to supporting the Virtex-5 LX and LXT FPGAs, version 8.2 of AccelDSP and System Generator also include support for the lower cost Spartan-3E FPGA family from Xilinx. These FPGAs are suited for cost-sensitive applications such as broadband access and home networking that not only require the parallelism of XtremeDSP technology but also the lowest logic cost in order to integrate additional system features such as interfaces, peripherals and control logic.

System Generator for DSP & AccelDSP
The new 8.2 version of System Generator enables DSP system and algorithm developersthat do not write VHDL or Verilogto develop their designs using MATLAB and Simulink from The MathWorks. Once floating-point modeling is complete, designers quantize it using the Xilinx bit- and cycle-accurate blockset and automatically generate HDL/RTL, netlists or complete bit streams for Xilinx FPGAs, including the new Virtex-5 LX and LXT devices. Finally, designers verify and debug the design on the actual FPGA using high-bandwidth hardware-in-the-loop simulations from within the Simulink environment. New to this release is FIR Compiler 2.0. This parameterized FIR filter complier extends previous versions by adding symmetric coefficient optimization for multi-rate filters reducing DSP48 resources by 50 percent.

AccelDSP is said to be the industry's only tool that enables DSP designers to develop algorithms using MATLAB and synthesize them into RTL. The tool enables automated floating-point to fixed-point generation providing both fixed-point MATLAB and C/C++ simulation models. It also offers algorithmic exploration that lets engineers make tradeoffs between sample rate, performance and area, and provides automatic test bench generation. Once RTL has been generated using the AccelDSP tool, a System Generator library block can be created for integration into a larger system. New to the 8.2 release is the inclusion of the AccelWare Algorithmic IP.

In addition, new pricing and packaging for AccelDSP provides a 50 percent cost saving on the tool when purchased separately and more than 60 percent saving when purchased as part of a complete Model-Based Design software package.

Standalone pricing for System Generator starts at $995 and AccelDSP is priced at $4,995. Both are available today. For free 30-day evaluations, visit System Generator and AccelDSP.




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