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Clear Shape offers electrical DFM analysis solution

Posted: 04 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Clear Shape? OutPerform? InShape? electrical DFM? DFM analysis?

Startup Clear Shape Technologies Inc. has announced OutPerform, said to be the first complete and silicon correlated electrical DFM analysis and optimization product to enable designers using sub-90nm processes to optimize and control the impact of lithography, mask, etch, RET, OPC and CMP effects on their chip parameters. OutPerform plugs directly into the designer's existing flows for cell design, IP, custom analog and cell-based digital design.

OutPerform takes in the chip designers' timing and place and route data, along with encrypted fab technology files, and identifies timing and leakage parametric hotspots for violations due to systematic variations. It produces timing optimization directives that drive the place and route tools. OutPerform gets its silicon-accurate critical dimensions (CD) for devices and interconnects from Clear Shape's InShape, which delivers accurate full-chip contour shape predictions across the process window in a matter of hours.

At 90nm and below, systematic variations are the greatest cause of chip failures, causing electrical issues such as timing, signal integrity and leakage power. For example, at 65nm, systematic variations of 3nm on a transistor gate can cause a 20 percent variation in delay and have a 2x impact on leakage power.

Over-design
With traditional corner-based design methodologies, margins are applied everywhere regardless of context. This over-design with excessive guardbanding stalls timing closure, and can still result in unexpected parametric failures due to unforeseen systematic manufacturing variations. Furthermore, over-designing to avoid DFM issues results in penalties to both area and leakage power.

With in-context model-based electrical DFM that incorporates fab technology information on lithography, RET, OPC, CMP, mask, and etch, chip designers can optimize their electrical parameters on-the-fly without any change to their library layout characterization, and tighten their design parameters knowing that the impact of variability has been carefully managed.

OutPerform fits into existing place and route and layout design flows and provides a closed loop between design and manufacturing. Cell-based chip designers input their DEF, SPEF, library information and fab DFM technology files into OutPerform. It is fast enough to quickly iterate with place and route: designers tighten their design margins, run place and route, then use OutPerform to identify hotspots and produce optimization directives. OutPerform also calculates the change in delay and timing skew based on the in-context shape variations and provides delay variations back to static timing analysis tools in the form of an incremental SDF. Therefore designers can verify and minimize the effects of variations on their cell-based design performance in their current design flow.

Place, route, layout
For custom design, OutPerform takes in a Spice netlist and Spice models and predicts current density across channels, extracting transistor parameters for transistors from the embedded InShape model-based silicon contour predictions. OutPerform then produces a back-annotated transistor Spice netlist. It also applies the changes in RC data to the designer's existing DSPF or SPEF file to represent the true effects of in-context silicon shape variations, without creating new nodes or parasitic elements. Designers can then simulate the back-annotated transistor Spice netlist with their Spice simulator to check the effect of variations on their design and detect potential failures undetected by conventional tools and before going to silicon.

Pricing starts at $300,000 per master license per year. OutPerform is available on Linux platforms. Distributed Processing is also available at incremental pricing.




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