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Renesas adopts Synopsys' VCS verification solution

Posted: 10 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:verification? VCS? VMM methodology? advanced SoC? SystemVerilog?

Synopsys Inc. announced that Renesas Technology Corp. has adopted the VCS functional verification solution for the development of complex SoC and VMM methodology for the creation of advanced SoC verification environments. Renesas used the VCS solution with the VMM methodology to verify its critical SuperHyway bus on-chip interconnect infrastructure.

"SystemVerilog and the VMM methodology have proven easy to adopt and deploy with the VCS solution, and will enable significant improvements in verification productivity in our Soc designs using the SuperHyway bus," said Kazunobu Morimoto, group manager, system level design and verification technology department at Renesas, in a statement.

The SuperHyway bus is a VSIA/VCI compliant on-chip interconnect infrastructure designed to give developers a scalable high-bandwidth, low-latency interconnect. Renesas needed to improve the productivity and predictability of the SuperHyway bus verification environment to keep up with growing demand for new system components. Their new environment needed to reuse legacy tests, enable detailed verification-progress tracking using coverage, and allow for easy addition, modification and maintenance.

"Renesas has proven that SystemVerilog and the VMM methodology can greatly improve verification productivity, while being easy to adopt and deploy," commented George Zafiropoulos, vice president of marketing, verification group at Synopsys.




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