Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

View from assertion-level logic

Posted: 01 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:assertion-level logic? circuit diagram? standard symbols? tilde character? Clive Maxfield?

The purpose of a circuit diagram is to convey the maximum amount of information in the most efficient fashion. One aspect of this is that the signals carried by the wires may be active-high or active-low.

To convey as much information as possible, it is preferable to indicate the nature of an active-low signal in its name. One method of achieving this is to prefix the name with a tilde character "~", such as ~enable.

The problem with the standard symbols for BUF, NOT, AND, NAND, OR and NOR is that they are tailored to reflect operations based on active-high signals being presented to their inputs. In some cases, this may not be appropriate, so special assertion-level-logic symbols can be used to more precisely indicate the function of gates with active-low inputs. For example, consider how we might represent a NOT gate used to invert an active-low ~enable signal into its active-high enable counterpart.

Both symbols indicate an inversion, but the assertion-level symbol is more intuitive in the case of this example because it reflects the fact that an active-low input is being transformed into an active-high output. In both cases, the small circles known as bobbles (or bubbles) on the symbols indicate the act of inversion. One way to visualize this is thatin the case of the standard symbolthis was formed with a BUF gate being followed by (driving) a NOT gate, and the NOT symbol has been pushed into the output of the BUF symbol until only the NOT's bobble remains visible. By comparison, the assertion-level symbol may be visualized as being formed from a NOT gate driving a BUF gate. In this case, the NOT has been pushed into the input of the BUF symbol until only the bobble remains visible.

In the real world, both standard and assertion-level symbols are implemented using identical logic gates. Assertion-level logic does not affect the final implementation, but simply offers an alternative way of viewing things. Visualizing bobbles as representing inverters is a useful technique for handling more-complex functions. Consider a portion of a circuit containing a tristate buffer with an active-high control input called enable. The enable signal is to be set to its active-high state if either of two other signals, called ~enable-A and ~enable-B signals, are in their active-low states.

Remember that both of these circuit representations are functionally identicalyou can easily prove this by drawing out their truth tables. However, the assertion-level representation is more intuitive, especially for someone who is unfamiliar with the function of the circuit. This is because the assertion-level symbol unambiguously indicates that enable will be set to logic 1 if either of the ~enable-A or ~enable-B signals is presented with logic 0s.

Any standard primitive gate symbol can be transformed into its assertion-level equivalent by inverting all of its inputs, exchanging any & (AND) operators for | (OR) operators (and vice versa), and inverting its output. In fact, these steps are identical to those used in a DeMorgan Transformation. Thus, assertion-level symbols may also be referred to as DeMorgan-equivalent symbols. The most commonly used assertion-level symbols are those for BUF, NOT, AND, NAND, OR and NOR.

- Clive Maxfield
Programmable Logic DesignLine




Article Comments - View from assertion-level logic
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top