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Panelists call for front-end design overhaul

Posted: 05 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DesignCon? IC? IC design? design flow? verification tools?

Asked "why are we still designing like it's 1992," panelists at the DesignCon conference mostly said that things aren't that bad. But they called for major upgrades to a front-end IC design flow that's increasingly dominated by power concerns.

Steve Carlson, vice president of product marketing for the design implementation division at Cadence Design Systems, said there's a "striking similarity" to design methods applied in 1995 and design methods used today. "Front end designers have somehow had a hall pass from having to evolve their methods," he said. "That's going to change, and one reason is power and the interrelationship of power to everything you do in design."

Many design teams are applying hefty margins and over-designing their ICs, Carlson said. "It's clearly time for an evaluation of how we apply margins in design, and power is a big impetus for that," he said. Carlson argued that power concerns must be brought forward in the design cycle. "If you relegate power to the back end, you can't explore different power architectures."

The IC design flow hasn't changed much, but architectures have, said Gagan Gupta, director of multimedia at ARC International. He said that fixed processors limit innovation, and that 20th century CPUs are not suited to today's applications. Gupta said that acceptance of reconfigurable processors is growing, along with tools that let users configure and optimize processors for their specific applications.

Paul Platt, director of design services at Integrated Device Technology, came with a list of ways in which the design flow has improved. He said that design software has more capacity, compute hardware is faster, verification is "massively better," back-end power analysis is much better, and tools comprehend the "new physics" of 65nm.

On the other hand, Platt said custom IC design has changed little in the past decade, leakage has become a huge issue, and there's too much after-the-fact analysis. "There's not a lot of good analysis on the early front end," he said. "I want to pull information forward and make early estimates, but it's just not there."

Design methodologies at NEC Electronics have changed dramatically, said Kazu Yamada, vice president and general manager for NEC Electronics America. He said that NEC started to use behavioral synthesis and co-verification tools in 2005, and that NEC's digital entertainment platform designs are now done in SystemC. Engineers can verify entire systems before hardware/software partitioning, do the partitioning, and then put the hardware part into RTL, he said.

Yamada acknowledged that "it's still a very messy process." There's a lot of discussion about what should be done in RTL, he said. Meanwhile, he said, embedded software development is becoming a bottleneck. "We have to have ways to let the software guys start before the chip is available," he said.

In some ways, EDA has progressed significantly, observed Brendan Farley, CTO at design house Silicon and Software Systems. He noted that RF and mixed-signal circuitry can be integrated into large systems-on-chip, that considerable intellectual property is available, and that it's possible to synthesize flat multi-million gate designs.

However, Farley said that IC physical verification has remained static and that it continues to use a rules-based approach. "It's too late in the design process," he said. "We need to take DFM [design for manufacturability] into account earlier in the design."

Returning to a common theme on the panel, Farley talked about the demands of low-power design and the impact of leakage at 90 nm and below. 10 percent of the transistors may consume 90 percent of the leakage power, he noted. "We have to change the design approach from a power perspective," Farley said.

- Richard Goering
EE Times




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