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Device-native verification tool rolls for FPGAs

Posted: 25 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA verification tool? Altera Stratix II? Xilinx Virtex-4?

There are far more FPGA design starts than ASIC design starts, but far fewer FPGA verification tools. Startup GateRocket Inc. steps forward this week to fill that gap with a "device native" FPGA verification solution that includes hardware and software.

"People have been aggressively developing FPGAs, but they're having significant difficulty with the verification process. It's slow, it's complicated, and it's inaccurate," said Dave Orecchio, GateRocket president and CEO. "We believe there's a significant and unserved market of people doing FPGA designs, and we believe we have something that's different from anything out there."

What GateRocket has is RocketDrive, a box that contains either an Altera Stratix II or Xilinx Virtex-4 FPGA. It hooks up to a Linux PC over a PCI cable. RocketDrive claims to validate designs 10 to 100 times faster than software simulation, while running as part of the customer's simulation environment.

Rocket's story
The six-person company got its start in 2004 because a chip designer made a painful transition from ASIC to FPGA design. That was co-founder Chris Schalick, now VP of engineering and chief technology officer. While working at Teradyne, Orecchio said, Schalick had a lot of difficulty getting FPGAs to work properly in the lab because he lacked clear visibility into what was happening inside the devices. So Schalick left Teradyne, developed the concept behind RocketDrive, and launched the company.

Orecchio joined in 2006 and helped line up $1.25 million in angel investments. Orecchio is a long-time EDA veteran who previously held sales and marketing positions at Viewlogic, Synopsys, Innoveda, Parametric Technologies and DAFCA. Alain Hanover, original chairman of Viewlogic, is chairman of the board of GateRocket.

RocketDrive, available now for shipment, claims to let designers exhaustively validate and test an FPGA design before committing to production. GateRocket's software lets users load portions of the FPGA design into the RocketDrive, using the customer's FPGA implementation tools, and then link it to the user's existing simulation platform. Designers can speed verification by running on actual hardware, investigate bugs and try alternatives, and run application-level software against a "device native" representation of the design.

A distinctive aspect of RocketDrive, Orecchio said, is that "we bring it into the loop of simulation. I don't have to change anything with regard to my testbench or my design methodology. I can gain the speed benefits of the RocketDrive and the accuracy of true chip behavior, with all the capabilities of my simulator."

Problematic boards
FPGA designers today often use evaluation boards to verify designs. One problem with such boards, Orecchio said, is that there's a fixed pinout for the FPGA. Secondly, he said, the design loaded into the FPGA is at the gate level, and even if you can see what's going on inside the chip, it's not related to your RTL code.

"Once you move into the lab, you lose all the power you had in your simulation and verification environment," Orecchio said. "You don't have the visibility, you don't have the context of signal names, and you don't have the debug ability." RocketDrive provides those capabilities, he said. "In essence, what we've done is brought the lab into the verification environment."

RocketDrive users start the verification process by loading some or all of their RTL design into the device, along with their simulation testbench. The user's own tools are used to synthesize, place and route the Xilinx or Altera FPGA. The RocketDrive can be programmed for any pinout configuration. From then on, said Orecchio, it just runs as part of the customer's simulation environment, with all the debug features of the simulator.

There are several use models, Orecchio said. One is the acceleration of simulation regression testing. Another is validation of third-party intellectual property. Yet another is verification of synthesis, placement and routing, providing a capability similar to the formal verification used in ASIC design flows.

RocketDrive can be installed in less than half an hour, Orecchio said. "Our promise to customers is that any FPGA ready design can be loaded into RocketDrive in a morning or less, and most of that is spent running vendor tools," he said.

Priced starting at $25,000, RocketDrive is for the high end of the cost-sensitive FPGA design marketplace. GateRocket, which contracts out the manufacturing, plans to sell through value-added resellers (VARs) and will initially focus on North America only. Meanwhile, GateRocket has launched an FPGA verification blog.

- Richard Goering
EE Times




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