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16Mbit SDRAM design cuts SiP/MCP costs

Posted: 02 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:16Mbit SDRAM design? DFT architecture? SiPFLOW platform?

Optimized for the mobile handset market, Inapac Technology Inc. is sampling a 16Mbit SDRAM design based on its high-volume SiPFLOW platform that incorporates a design-for-test (DFT) architecture and production methodology.

According to Inapac, the SiPFLOW platform enables SiP and MCP producers to minimize cost of ownership while achieving production quality and reliability. The total cost of incorporating the 16Mbit memory die would be less than 50 cents per SiP/MCP in volume production, further extends their reach in high-volume consumer markets where their average selling price is $5 or less, the company said.

Inapac's SiPFLOW platform is licensed to SiP and MCP suppliers addressing such applications as feature-rich cellular handsets, personal media players and LCD-based displays.

"The new design enables smaller packages, lower power and lower-cost implementations," said Naresh Baliga, VP of marketing for Inapac, in a statement. "The new design offers a bond-pad-compatible transition from the existing design, and is manufactured on the proven, high-volume 0.12?m DRAM wafer foundry from ProMOS Technology."

- Gina Roos
eeProductCenter




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