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USB PHY trims power in 65nm, 45nm SoC designs

Posted: 07 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:USB PHY core? USB 2.0? IP cores? 90nm?

Analog/mixed-signal merchant IP supplier Chipidea introduces a USB PHY core for 1.8V I/O devices that it says offers the industry's lowest power consumption for SoC designs in the 65nm and 45nm advanced technology nodes.

The Chipidea architecture provides a power consumption of approximately 70mW. Fully compliant with the USB 2.0 specification, Chipidea's 1.8V USB PHY guarantees D+ and D- protection to withstand transient short-circuit voltage without damage. The core also features analog programmability for fine-tuning.

The IP is available as a standalone PHY or matched with a USB controller.

"We are offering a new generation of USB IP cores using 1.8V devices for designers that require the lowest power consumption," said Celio Albuquerque, division director of Chipidea's physical solutions division. "This 1.8V platform extends our portfolio to a new I/O device choice, while maintaining the advantages of our IP, including analog programmability, BIST and full USB2.0 compliance."

Chipidea's certified USB cores are available at several of the industry's leading foundries and advanced process nodes. The IPs have been certified to provide design flexibility in the 0.18?m, 0.13?m, 90nm and 65nm process nodes.

- Ismini Scouras
eeProductCenter




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