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Embedded eyes multicore to save power

Posted: 28 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:embedded multicore? processors? save power? 65nm?

Like their microprocessor-making cousins in the X86-based PC world, suppliers of high-end embedded processors appear to be raising the white flag in the breakneck megahertz race. Instead of focusing on raw performance alone, suppliers are now racing to develop a range of 32- and 64bit multicore solutions that claim to address a potential power crisis in the high-end embedded space.

In the latest developments in the emerging sector, Cavium Networks Inc. and Freescale Semiconductor Inc. on Monday (June 25) has scheduled to separately introduce major multicore processor lines for high-end embedded applications. The products provide a sneak preview of next-generation multicore architecturesand the challengesin the networking, storage, wireless and other embedded markets.

Dash to multicore
Startup Cavium will roll out an embedded-processor line for the storage and communications markets, based on a 64bit architecture from MIPS Technologies Inc. Reportedly seeking to play catch-up in the market, rival Freescale is to launch a next-generation multicore platform built around the PowerPC-based Power Architecture. Its new platform is based on a 45nm process and silicon-on-insulator (SOI) technologyin this particular segment, Freescale appears to be skipping the 65nm node.

AMCC, Broadcom, Intel, PA Semi, Raza and other vendors have recently introduced single or multicore embedded processors for networking, storage, wireless and related high-end applications, all for a good reason: This chip market could exceed $3 billion by 2010.

The vast majority of OEMs still procure single-core, 32- and 64bit solutions, but the market dynamics are rapidly changing. "In the high-end embedded space, we're hitting the wall in power dissipation," said Linley Gwennap, president and principal analyst of the Linley Group.

Higher-end communication systems such as base stations, DSL equipment and routers generally have power budget requirements of up to 15-20W, Gwennap said. But OEMs are generally tapping out on these budgets, forcing them to look at new multicore solutions to address the growing power-efficiency problems in system design, he said.

Hurdles, challenges
Embedded multicore solutions have been around for some time. But for power efficiency and other factors, the newfangled ones are moving from the early-adopter stage to the mainstream, said Amer Haider, director of strategic marketing at Cavium.

Scaling is far from dead, but the megahertz race at the high end of the embedded market appears to be winding down.

This trend resembles the PC-based processor market. For years, Intel claimed it could boost the clock speeds in a processor to 10GHz or more, but power dissipation remained a huge stumbling block. AMD and Intel were forced to end the megahertz race in the PC market in favor of multicore solutions. A multicore product takes existing processor cores and scales them in an SoC configuration, thus reducing chip count and power. Multicore products are also supposed to split the functions among the cores, making the system more efficient.

At the heart of Freescale's platform is a new scalable fabric technology for on-chip connectivity.

But unlike the PC market, the embedded multicore business presents a slew of new and confusing choices for high-end OEMs. The vast majority of OEMs still procure ASICs, DSPs, FPGAs and general-purpose single-core processors. In fact, the majority of applications will not require multicore solutions for the foreseeable future.

But the sudden emergence of multicore embedded processors pits a growing number of large players and startups against a range of competitive architectures, including those based on ARM, MIPS, PowerPC, X86 and others.

It's also unclear if these solutions can take advantage of the inherit parallelism within the various architectures. In fact, officials from Freescale claim that the first-generation multicore architectures have experienced mixed results. Some products are overkill for most applications; still others are unable to run legacy software, they said.

But given the growing amount of data flowing in the infrastructure today, "We're at an inflection point," said Jeff Timbs, marketing director in the Network Systems Division at Freescale. System designers are looking to "leverage dual-core and then multicore architectures to solve their next-generation challenges."

Competing solutions
In 2005, Freescale rolled out dual-core versions of its PowerQuicc communications processors. The latest PowerQuicc products are based on a 90nm SOI process. Going forward, Freescale appears to be skipping the 65nm step and jumping directly into 45nm. Slated for delivery in late 2008, its 45nm, SOI-enabled platform will be based on a process technology from IBM Corp.'s common platform alliance.

Compared with 90nm technology, the 45nm version is said to improve power performance by 50 percent. The platform can support over 32 homogenous and heterogeneous cores, including a DSP. The platform is expected to support its existing 1.5GHz core, dubbed the e500-mc.

At the heart of the platform is a new scalable fabric technology for on-chip connectivity. The platform also supports Ethernet, PCIe and Rapid I/O.

Freescale's new rival in the area, Cavium, is rolling out 90nm versions of its Octeon multicore line for the networking space. Separately, it is also entering the storage processor market with new versions of its Octeon line. Built around a 90nm process from TSMC, the Octeon Storage Services Processor family is based on a 64bit, RISC-based architecture from MIPS Technologies.

The processor line, which consists of seven devices, can be scaled from two to 12 cores. The devices also feature storage application acceleration, 10Gbit Xaui, PCIe, GbE ports and dual DDR2 memory. Applications include Fibre Channel and Ethernet disk arrays, RAID controllers, multiprotocol switches and iSCSI adapters. Prices range from $59 to $575 in 10,000-unit quantities.

- Mark LaPedus
EE Times




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