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Overcome high-speed FPGA design challenges

Posted: 01 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:PCB FPGA design issues? board design? high-speed FPGA design?

As FPGAs have evolved into true programmable SoCs, the task of designing the PCBs on which these chips are used has become more complex. Multimillion-gate densities, transceiver data rates above 6Gbps and other considerations affect the mechanical and electrical board-design efforts of system developers. The die, chip package and board form a closely coupled system in which careful PCB design is needed to fully realize the capabilities of an FPGA.

When using high-speed FPGAs in a design, it is important to consider certain issues both before and during board development. These include reducing system noise by filtering and evenly distributing sufficient power to all devices on the PCB; properly terminating signal lines to minimize reflections; minimizing crosstalk between board traces; reducing the effects of ground bounce and Vcc droop (also called Vcc sag); and properly matching impedances on high-speed signal lines.

It takes special care designing an IC package for a very high-performance FPGA to balance signal integrity with versatility for all users and applications.

The user can play a role in crosstalk reduction during the pin assignment phase of the design. It is advantageous to choose signal pins as close as possible to ground pins for short loop lengths within the package, specifically for critical high-speed I/Os. In high-speed systems, a significant source of crosstalk is inductive coupling between signal paths within the package. As outputs switch, the signal must find a return path through the power/ground planes. The changing current through this loop creates a magnetic field that induces noise on other I/O pins in the vicinity of the loop. The situation is exacerbated for simultaneously switching outputs. Because a smaller loop has less inductance, a package that provides a power or ground pin close to every high-speed signal pin minimizes the impact of crosstalk on nearby I/O pins.

Minimizing board cost and maximizing system signal integrity for all the signal paths requires that the board materials, number of layers (stack-up) and layout be carefully designed and constructed. Trying to route several hundred signals from the FPGA to and around a board is a difficult task, requiring the use of an EDA tool that can optimize pin assignment and chip placement. Sometimes using a slightly larger FPGA package can reduce board cost, since it may reduce the number of board layers and other board-manufacturing constraints.

To improve the signal integrity of the clock signal, follow these guidelines:

  • Keep the clock signal on a single board layer if possible until it is routed to board components; always reference a plane, as a minimum.

  • Route any fast edge signal on an inner layer adjacent to a ground plane, to control the impedance and reduce EMI.

  • Correctly terminate clock signals to minimize reflections.

  • Point-to-point clock traces are best.

The user can play a role in crosstalk reduction during the pin assignment phase of the design.

The following are suggestions for microstrip or strip line routing:

  • Keep trace spacing at least three times the thickness of the dielectric layer between board routing layers; best practices use simulation tools to anticipate behavior.

  • Use differential in place of single-ended topology for critical high-speed nets to minimize effects due to common-mode noise. Closely match the positive and negative legs of differential-signal paths within design limits.

  • To reduce coupling effects on single-ended signals, space appropriately (>3x the width of traces) or route them on different board layers (orthogonal to each other for adjacent layers). Again, simulation tools are the preferred method for spacing requirements.

  • Minimize parallel run lengths between single-ended signals.

As clock and I/O data rates increase, there is a corresponding decrease in output switching times and an increase in transient currents during the discharging and charging of the signal path. These currents may cause board-level ground bounce, a transient rise/fall in the voltage level of a ground/Vcc net as seen by the board's components. High transient currents from a non-ideal power supply result in the transient drops in Vcc.

These good board design practices can reduce simultaneous-switching-noise effects:

  • Configure unused I/O pins as output pins and drive pins low to reduce ground bounce.

  • Minimize the number of simultaneous-switching output pins and distribute them evenly throughout the FPGA I/O banks.

  • Use the slow-slew-rate option on FPGA outputs when fast edge rates are not required.

  • Sandwich Vcc to ground planes on multilayer boards to decouple high-speed traces on different layers.

  • Dedicating entire board layers to Vcc and ground minimizes the resistance and inductance of these planes. This provides a low-inductance source of capacitance and noise reduction, and a return for logic signals on signal layers adjacent to these planes.

EMI due to a PCB is directly proportional to a change in current or voltage over time, and also to the series inductance of a circuit. Effective board design can minimizebut not necessarily eliminateEMI. Burying "aggressor" or "hot" signals and routing signals appropriately referenced to ground planes can also help reduce EMI. Lastly, although it is commonplace in today's marketplace, the use of surface-mount components is also a factor in EMI reduction.

Debugging and testing complex, high-speed PCB designs has become increasingly more difficult, since some traditional board debug methodssuch as test probes and "bed of nails" test fixturesmay not be feasible for these designs. This new class of high-speed designs can make use of JTAG test access for in-system programming and many built-in self-test features that might be available within the FPGAs. Designers should use the same guidelines for laying out the JTAG test clock input signal as the system clock. To minimize delays between the FPGAs, it's also important to minimize the JTAG scan chain trace length between the test data output of one device and the test data input of another.

- Joel Martinez
Senior Product Marketing Manager, High-density FPGA Products
Altera Corp.




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