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PCI SIG sets PCIe 3.0 at 8GTps

Posted: 10 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:PCIe 3.0? PCI SIG? 8GTps rate?

Putting a stop to the long debate on the bit rate for the next-generation PCI Express (PCIe) interconnect, the PCI Special Interest Group (PCI SIG) has finally set 8GigaTransfers/second (GTps) as the bit rate for the 3.0 version.

Some engineers argued a higher throughput was needed to make sure the next step delivered enough performance to make it worthwhile. Ultimately a concern over costs and compatibility drove engineers to decide on a more modest step forward.

As a compromise, developers agreed PCIe 3.0 will remove the 8bit/10bit encoding in the existing technology. That will remove processing overhead of as much as 20 percent, opening the door to real throughput of about twice the maximum that can be attained through the 5GTps version 2.0 announced in January.

Instead of 8bit/10bit encoding PCIe 3.0 will use an existing scrambling-polynumial technique with fixed-length packets at the beginning and end of data flows. The technique helps handle clock recovery and resolve the DC wandering issue without generating bandwidth overhead. The method does, however, require additional processing power in the media access controller.

The slower, the better
The PCI SIG studied the data rate issue for about six months, concluding the slower rate was a better fit both for mainstream silicon process technology and available materials for printed circuit boards. The group was also concerned that a 10GTps version might not be compatible with the original 2.5GHz Express spec in wide use today. In addition, its research showed the power requirements for moving from 8GTps to 10GTps increased exponentially rather than in a linear fashion.

"I had a lot of people coming to me at IBM asking when the decision would be made," said Al Yanes, chairman of the PCI SIG and an ASIC development manager at IBM. "A lot of the high speed interfaces such as Ethernet, Fibre Channel and Infinibandas well as graphicsneed to know how much I/O you can run across the pc board so they can work out their own road maps," he added.

Enhanced features
PCI Express 3.0 will include a variety of new features such as enhanced signaling and data integrity, transmit and receive equalization, PLL improvements, clock data recovery and channel enhancements. The group expects a final spec could be available by late 2009 with products emerging the following year.

In addition, 3.0 will be the first version of the interconnect to use Decision Feedback Equalization (DFE), Yanis said. It will use a linear, multi-tap version of the technology on both the receiver and transmitter, he added.

An anonymous comment on the EE Times interconnect blog criticized the choice of linear DFE. Such a link will not be able to support economically the non-linear equalization techniques used by many 10G standards including CEI-6LR, 10Gbase-KR, XFI, CEI-12SR/LR and others.

"Not having the volumes of PCI Express will delay development of many 10G standards. Given that we're seeing 3-4 years between PCI Express standards, we're probably looking at a delay of 3-4 years for these 10G standards," the commenter wrote.

More research
An initial, early version of the spec will be released to PCI SIG members before the end of the year. The group typically develops five rounds of draft before a spec is complete. Before the new version is released, engineers plan to refine electrical parameters of the spec based on simulations and test silicon developed by multiple SIG members.

Meanwhile, the group expects the first wave of PCI Express 2.0 products will be broadly available in the market by the end of this year. However, it's not clear whether future on-board interconnects from the PCI SIG will still be able to use copper traces.

"I keep hearing about optical carriers, but we are not sure," said Yanes. "We have more research to do on that. Two years ago we might not have thought we could hit this 8GTps data rate," he added.

- Rick Merritt
EE Times

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