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PCIe 3.0 draft spec triggers debate

Posted: 14 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:draft spec? PCIe 3.0? technical debate?

A debate on some of the technical decisions behind the draft specification for PCI Express 3.0 has surfaced within hours of the announcement of the first details of the draft spec.

The PCI Special Interest Group (PCI SIG) announced Wednesday that PCIe 3.0 will target a theoretical maximum throughput of 8GTps, double the actual max throughput for today's PCIe 2.0. In addition, it will be the first version of the interconnect to use a multitap version of linear Decision Feedback Equalization (DFE) on both the receiver and transmitter.

An anonymous comment on the EE Times interconnects blog criticized the choice of linear DFE. Such a link will not be able to support economically the non-linear equalization techniques used by many 10G standards including CEI-6LR, 10Gbase-KR, XFI, CEI-12SR/LR and others.

"Not having the volumes of PCI Express will delay development of many 10G standards. Given that we're seeing 3-4 years between PCI Express standards, we're probably looking at a delay of 3-4 years for these 10G standards," the commenter wrote.

Donald Telian, a signal integrity consultant, pointed out that it is unfortunate the industry isn't aligning on one road map for complex core technologies such as Serdes and equalization. However, there's nothing really new in that, he said.

PCIe 1.0 ran at a maximum 2.5G when telecom was at 3.125G. It officially jumped to a 5G version 2.0 in January when telecom was at 6.5G, and the score for the next round will be PC 8G and Telecom 10G. It's just a reality that PCs want low cost to drive high volume and telecom will pay for high performance.

As for equalization, this is still more a secret sauce than a solved problem, said Telian, who is not a member of the PCI SIG but said he understands their reasoning.

"We do not see this as an issue to the spec, but rather a concern about other industry effects associated with our decision for 8GTps," said PCI SIG chair Al Yanes in an email.

"The industry has several PHY strategies," said Yanes. "Some vendors develop generic cores that meet multiple solutions to maximize their development expenses and there are other core developers that do specific cores for specific markets to get the optimal design of power and die size area. The industry is large enough to support both business models," he said.

- Rick Merritt
EE Times

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