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Off-chip ESD protection anticipates IC scaling

Posted: 16 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:off-chip ESD protection? transient voltage suppression? clamping voltage? submicron ICs?

As next-generation transceivers and digital communications ICs scale to smaller geometries, the challenge for IC manufacturers to maintain reasonable levels of on-chip ESD protection becomes greater. Proposed decreases in on-chip ESD protection mean that system designers must be more aware of building ESD protection into their designs by choosing the right devices and following key design principles.

In the race to provide more and faster functionality, on-chip ESD protection is often sacrificed in favor of chip performance. According to the ESD Association, the ICs of tomorrow will not sustain the current levels (2kV) of on-chip ESD protection. In fact, there is a proposal to lower on-chip ESD stress target levels by more than half. At the system level, as on-chip protection is reduced, ICs will be more sensitive to transients such as cable discharge events and ESD from the human body. With increased ESD sensitivity of current and future ICs, the need to protect systems with more robust off-chip transient voltage suppression is greater than ever.

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