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Xilinx teams with EDA giants on 65nm FPGA verification

Posted: 17 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:verification teams? 65nm Xilinx FPGA? EDA giants?

Xilinx Inc. has announced a collaboration with three major EDA companiesCadence Design Systems Inc., Mentor Graphics Corp. and Synopsys Inc.to address the challenges of ultrahigh-capacity FPGA design verification.

The collaborating companies intend to define and implement new verification flows to maximize productivity and quality of results for ultrahigh-density designs targeting today's 65nm FPGAs as well as new and emerging FPGA architectures. The collaboration will focus on expanding coverage, improving simulation runtime and reducing verification time in an environment that allows designers to achieve aggressive design goals. Major releases of these tools and methodologies are expected in 1H 2008.

"With the growing complexity of today's 65nm FPGAs, verification has become a major time consuming portion of the FPGA design flow," said Bruce Talley, VP of the Design Software Division at Xilinx. "By collaborating with the industry's leading EDA providers, we can develop solutions to address the challenges faced by our customers at 65nm and beyond."

Xilinx introduced what it said to be the industry's first 65nm FPGAsthe Virtex-5 series, which have been shipping since May 2006. The platform includes devices with up to 330,000 logic cells, 10Mb on-chip memory, 1,200 I/Os and a host of additional hardened IP blocks. Ongoing growth trends in FPGA architecture present escalating challenges for logic designers with increasing density points and capabilities across a wide range of application domains. The companies will work together to build upon existing technologies to develop next-generation verification solutions, enabling system designers to streamline the verification process.




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