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Faraday unveils ARM v5-compliant processor

Posted: 17 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:ARM v5 processor? infotainment application? Faraday processors?

Faraday Technology Corp. has unveiled the FA626TE, its first ARM v5 instruction set architecture-compliant processor, which is a 32bit RISC promising excellent computing and power-efficient capabilities.

The FA626TE is specially designed for applications like infotainment systems, portable navigation devices, IP-STBs, industrial PCs, high-speed network and storage SoCs.

The FA626TE processor with eight pipeline stages has separate instruction/data caches and scratchpads, a write buffer, a memory management unit and a JTAG ICE interface. The FA626TE CPU core uses four AHB or AXI interfaces with configured 32/64bit widths to communicate with external memory and devices. For designers, the fully synthesizable core and the single-phase clock based architecture especially make the SoC integration a very easy task.

"To meet the high clock requirement of the powerful 800MHz FA626TE, we overcome the process and micro-architecture limitations by implementing several advanced design techniques," said Thomas Hsieh, associate VP of central R&D at Faraday. "We're developing the solution by using data path optimization, process tuning, specific library and bin sorting to improve core clock speed, but preserves portability and ease-of-integration. That's how we could implement the ultrahigh-performance FA626TE processor which enables the 800MHz speed in 90nm process." he added.

The first hard core which reaches the worst case clock speed at 533MHz is available in UMC 0.13?m process. Faraday expects its next versions for 90nm in UMC, running 667MHz and 800MHz in worst case, to be available in initial Q4 and the end of 2007, respectively.

Faraday will be participating at the 7th Embedded Systems Conference-Taiwan (ESC-Taiwan) and the 15th EDA & Test-Taiwan Conference & Exhibition (EDA&T-Taiwan on August 23-24 at the Taipei International Convention Center.




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