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AMD unveils code-reducing tech for x86

Posted: 04 Sep 2007 ?? ?Print Version ?Bookmark and Share

Keywords:x86 instruction set? code-reducing technology? microprocessor?

Advanced Micro Devices (AMD) has introduced the SSE5 code-reducing technology planned for its next-generation microprocessor expected in 2009.

An extension of its x86 instruction set, the specification is meant to maximize the efficiency of applications running on the platform by reducing the number of instructions needed to achieve a particular result.

Introduced in 1999, SSE, stands for streaming SIMD extension. SIMD, or single instruction multiple data, is the instruction set for the x86 architecture. The latest technology is designed to boost software performance through the use of special instructions that can operate on multiple pieces of data at one time. SSE is as important to software performance as are multicore processor technology and the integration of specialized co-processors, the company said.

SSE5 increases the number of inputs, or operands; an x86 instruction can handle from two to three. Such a capability is currently possible only on certain RISC architectures. In addition, the specification introduces "fused multiply accumulate," an instruction that combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, execution of complex vector mathematics, and other computing-intensive chores.

AMD has made SSE5 available to developers through its Website. AMD plans to implement the specification in its next-generation processor core, code-named Bulldozer.

- Antone Gonsalves
InformationWeek




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