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Keeping up with complex intellectual property

Posted: 16 Oct 2007 ?? ?Print Version ?Bookmark and Share

Keywords:intellectual property? DSP? embedded vector technology? verification techniques?

The verification of IP cores continues to become more complex and time-consuming, especially for processor cores, such as CPUs, floating-point units and DSPs. The challenge is to design and verify a new embedded vector processor with significant enhancements over its predecessor. This has been achieved by NXP's AdelanteTM VD3204x Embedded Vector DSP family. To improve the quality of the DSP technology at DSP-IC, a department within NXP, the attention for verification turned to tools and techniques that might advance the process.

NXP's embedded vector processor core is built on Very Long Instruction Word (VLIW) architecture to support a significant degree of parallelism for both scalar and vector operations targeted at various multistandard communication pipes, such as 3G/3.5G, WLAN and DVB. As such, the need for exercising many corner-case conditions during verification is a pre-condition. Users of DSP technology depend on receiving a robust core with the highest quality, so their focus can be entirely on the SoC design.

Given the complexity of the DSP architecture, the traditional approach using random-generated tests with a few functional coverage points became outdated. Consequently, the full plan-to-closure methodology is chosen using coverage-driven, constrained-random verification architecture. To do so, Cadence's Plan-to-Closure methodology, including the company's Specman Elite testbench automation solution and the verification management platform, was implemented.

The chosen methodology calls for the use of an executable verification plan (vPlan) as an alternative to old-fashioned paper-based test plans. The central idea is to identify verification and coverage goals early in the process, and then throughout the course of the project, report on progress against the established goals. The vPlan proved to be useful not only for verifying individual blocks, but also for integrating them into a major sub-unit or complete chip.

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