EDA's big three unready for 3D chip packaging
IMEC is putting a renewed emphasis on chip packaging¡ªand on 3D-integration in particular¡ªaccording to plans revealed at a press briefing before last week's Annual Research Review Meeting. However, IMEC and European chip company experts are not expecting much help to come from the "big three" EDA companies¡ªusually taken to mean Cadence Design Systems Inc., Mentor Graphics Corp. and Synopsys Inc.
This could slow down the adoption of beneficial approaches to system design that could take into account memories and processing cores distributed across multiple stacked die, according to panelists that convened to conclude the press meeting. But it is probably an inevitable consequence of the economics of EDA, which means the large companies are primarily interested in selling and supporting tools that are compatible add-ons to their established tool base and which are likely to ship to thousands of engineering seats, panelists suggested.
IMEC, foreseeing the rise of the multiple die system-in-package, has investigated packaging for a number of years. IMEC has now decided to open up a 3D-SOC design program to complement work on wafer-level packaging (3D-WLP) and stacked IC materials and processes (3D-SIC). IMEC is combining the three programs to foster an holistic approach to using the third dimension in chip and system design.
Eric Beyne, scientific director of packaging, interconnect and systems integration, described it as a "chicken-or-egg" problem. Without design tools to allow exploration and tradeoffs to be made in 3D layouts, engineers are restricted to design in two dimensions and occasionally stack chips crudely. But without a clear market for 3D design EDA vendors are unlikely to offer tools.
The new enlarged 3D research program at IMEC intends to produce a physical design flow for 3D that can include cost models that allow system-level tradeoffs to be made. It will use IMEC's software-defined radio and cognitive radio work as its application driver.
Beyne admitted that there is already quite a bit of chip stacking and wirebonding across multiple die already happening within industry. However, this tends to be confined to the stacking of memory die where the pin-outs are relatively simple and uniform. The introduction of wafer-thinning and through-silicon vias could allow stacking of logic ICs with implications for the shortest distance between logic blocks and performance " if tools could address this.
"It needs to be considered further back than place and route. You need to consider which blocks you want on which level of silicon," said Beyne. He described it as a 3D network on chip approach but indicated that individual blocks would probably still be designed in two dimensions. "You don't want to change IP blocks too much," he said.
When asked if the big-three or four EDA companies would be prepared to get involved with IMEC and help create such tools, Beyne said: "These companies are not going to drive the program. The companies that care about this are the system companies."
The same sentiments were expressed by panelists who joined Beyne in the last session of the press briefing. Fred Roozeboom, a research fellow with Dutch chipmaker NXP, argued that there is a need for fine-grained classification of interconnect within back-end of line and elsewhere and for road-mapping to help drive the opportunity to generalize and systematize 3D interconnect, but he added that progress would ultimately be cost-driven, just as Moore's law is cost-driven.
Jochen Reisinger, in charge of chip-package-board codesign at German chipmaker Infineon Technologies AG, agreed: "3D volume will come but it will take time. In 10 years the technologies will be ready and cheap, design systems will be ready and in use, because there are clear performance benefits." Reisinger's caveat was that in the case of testing and quality assurance it may still be necessary to stay with 2D design to provide access.
Reisinger also stressed the importance that a flow is created with manageable design tasks and standard data interfaces for hand-offs between engineers. "One guy working with one screen doing the whole 3D design will not come."
The panelists broadly agreed that EDA companies would need to be encouraged to engage with 3D design perhaps by way of lobbying being done through IDMs and industry groups such as the Fabless Semiconductor Association and the Silicon Integration Initiative.
Reisinger said there is little interest amongst the top EDA companies but added that is quite normal as EDA technologies usually get developed by startups who then get acquired by a large EDA vendor once the market reaches enough size to make it worthwhile. "The only interest [in 3D chip design] is from Zuken," Reisinger said.
- Peter Clarke
EE Times Europe
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