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Building PCIe endpoint devices with FPGAs

Posted: 03 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:PCI Express? PCIe endpoint devices? FPGAs? Ethernet? Alex Goldhammer?

PCIe is a high-speed serial I/O interconnect scheme that uses a clock data recovery (CDR) technique. The PCIe Gen1 specification defines a line rate of 2.5GBps per lane, allowing the building of applications that have a throughput of 2Gbps (after 8B/10B encoding) for a single-lane (x1) link to 64GBps for 32 lanes. This allows a significant reduction in pin count while maintaining or improving throughput. It also reduces the size of the PCB, the number of traces and layers, and

simplifies layout and design. Fewer pins also translate to reduced noise and EMI. CDR eliminates the clock-to-data skew problem prevalent in wide parallel buses, making interconnect implementations easier.

The PCIe interconnect architecture is primarily specified for PC-based (desktop/laptop) systems. But just like PCI, PCIe is also quickly moving into other system types such as embedded systems. It defines three types of devices: root complex, switch and endpoint. The CPU, system memory and graphics controller connect to a root complex, which is roughly equivalent to a PCI host. Because of PCIe?s point-to-point nature, switch devices are necessary to expand the number of system functions. PCIe switch devices connect a root complex device on the upstream side to endpoints on the downstream side.

View the PDF document for more information.




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