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Virtex-5 FPGA solutions fit SPI-4.2, SFI-4.1 interfaces

Posted: 06 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:SPI-4.2? SFI-4.1 interfaces? Virtex-5 FPGA?

Xilinx has announced complete solutions for the Optical Internetworking Forum (OIF) SPI 4.2 and SerDes Framer Interface (SFI) 4.1 standards, the industry's highest performance channelized packet interfaces.

Based on its high-performance Virtex-5 LXT FPGAs, these solutions feature the ML550 hardware verification board, SPI-4.2 LogiCORE IP and SFI-4.1 reference design. Verified across multiple FPGA platforms, the solutions accelerate the design cycle of wired networking systems that require OC-192 (10Gbps), multiple OC-48 (2.5Gbps) or 10Gbps Ethernet interfaces and are claimed to result in faster time-to-market than competing solutions.

The Xilinx ML550 board is said to be ideal for the development and evaluation of OIF and other networking interfaces, allowing designers to implement high-speed applications with extreme flexibility. Xilinx's ChipSync technology, available only in Virtex-5 FPGAs, provides accurate dynamic alignment of clock and data using 75ps programmable delays, enabling improved timing and reliable operation under changing system conditions.

The Xilinx SPI-4.2 LogiCORE IP, which is fully compliant with the OIF SPI-4.2 standard, interconnects PHY ASSPs to link layer FPGA devices in a wide range of networking applications and multiservice DWDM and SONET/SDH-based transport systems. The Xilinx SPI-4.2 IP core provides proven interoperability with industry leading ASSPs and is claimed to provide up to 20 percent higher data bandwidth due to optimized payload efficiencies as compared to competing FPGA offerings.

The Xilinx SFI-4.1 reference design supports up to 710Mbit/s/channel with dynamic alignment to provide a robust solution for OC-192 framer interfaces.

The SFI-4.1 reference design is immediately available free of charge. The SPI-4.2 LogiCORE IP is available for a free evaluation and can be purchased for an $18,000 site license fee.

- Clive Maxfield
Programmable Logic DesignLine




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