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Toshiba details 32nm advancements for system LSIs

Posted: 14 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:32nm technology? system LSI? metal gate?

Toshiba Corp. has unveiled advancements in three basic technologies for 32nm-generation system LSIs and beyond. The advancements cover improved metal gate electrode; new structure and process technology for low resistance contacts; and a technology for improving performance by changing the surface orientation of the silicon substrate.

The three technologies were introduced at the International Electron Devices Meeting conference, as major candidates for basic technologies for use in 32nm generation system LSIs and beyond. Toshiba will continue their development and optimization and aim for mass production in the first half of FY2010.

Challenges in 32nm generation system LSI development include minimizing electric resistance and improving performance. Achieving this is impossible without changes in basic materials and structures, and their optimization. Establishing the first metal gate technologies to be applied with 32nm generation, and minimizing contact resistance, and enhancing carrier mobility are imperative. Toshiba's achievements in solving these challenges bring other elemental advances into sight.

In developing the improved, new metal gate, Toshiba has realized a simplified manufacturing process technology that employs nickel silicide, a common material for both nMOS and pMOS transistors in a ratio of 1:3, respectively, and introduces an aluminum layer only in the nMOS gate.

For the low resistance contact, Toshiba employed a metal material in the source/ drain region, reducing contact resistance to a quarter in the nMOS side. The base electrode material is the same for both the nMOS and pMOS in pairs, and low-Schottky-barrier metal suitable for each type MOS transistor is segregated at interface of base material. The manufacturing process is simplified.

Since system LSI integrates CMOS elements, nMOS transistors and pMOS transistors, an optimized process is required. These new two technologies enhance performance and also contribute to an efficient manufacturing process.

The technology for changing the surface orientation of the silicon substrate rests on the fact that using the 110 surface improves hole mobility as compared to the usual 100 surface. The company found that both carrier mobility and gate capacitance increase in the 110 pMOS FETs, and demonstrated further improvement of drive current by 19 percent in a 32nm generation embedded-SiGe source/drain structure with 0.6 percent strain. In addition, the company found that the 110 pMOS FETs achieves six-times faster processing speed in ideal conditions.




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