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Perform low-power manufacturing test

Posted: 16 Jan 2008 ?? ?Print Version ?Bookmark and Share

Keywords:design-for-test process? DFT process? scan ATPG algorithms? low-power manufacturing tests? dynamic power consumption?

The very process of testing digital circuits routinely increases their dynamic power consumption to levels exceeding their power specification. If the power consumption is great enough, it can result in failures at wafer probe or pre-burn-in package test that require a significant amount of time and effort to debug. This issue, especially prevalent when testing very large SoCs under corner conditions, causes unnecessary yield loss on the production line and reduces manufacturers' gross margins. The best way to avoid test power problems is to incorporate power-aware testing techniques in the design-for-test (DFT) process. This article examines the relationship between dynamic power consumption and test to determine why managing power is more critical today than ever before. It also explores two DFT methodologies that take advantage of recent advances in ATPG technology to automate the generation of low-power manufacturing tests.

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