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Dual-core chips achieve 1,920 MIPS processing

Posted: 05 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:dual-core processors? symmetric multiprocessing? CPU cores?

SH-4A

Renesas Technology Corp. has developed the SH7786 Group of dual-core processors built around twin SH-4A CPU cores. The SH7786 Group is intended for high-performance multimedia systems, especially car information system (CIS) such as car navigation systems. It incorporates dual Renesas Technology SH-4A high-performance CPU cores to achieve superior processing power of up to 1,920 MIPS (when operating at 533MHz).

For its two CPU cores, the SH7786 Group uses the SH-4A CPU core available in the SuperH family of 32bit RISC microcomputers, and newly adopted a core architecture that supports a dual-core configuration.

The SH7786 Group supports both symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP), allowing both CPU cores to handle a single processing task using parallel processing for improved efficiency. This results in a maximum processing performance of 1,920Mips. The SH7786 Group can handle the high-speed processing of complex data necessary to meet the requirements of next-generation car navigation systems with functions such as graphical display capabilities, high-quality audio reproduction, and image recognition, while also reducing power consumption.

Product features
The SH7786 Group integrates dual SH-4A CPU cores on a single chip. The SH-4A is a 32bit RISC CPU core consisting of a CPU and FPU that are backward compatible at the instruction set level with SH-1, SH-2, SH-3 and SH-4 microcomputers from Renesas Technology.

The device's clock frequency and low-power mode can be set independently for each CPU, making it possible to minimize power consumption while responding to changes in the processing load.

The SH7786 Group also enables rapid development of distributed function systems employing multicore technology and support for highly reliable operation. In a distributed function system using a multicore device, the individual subsystems having different characteristics and functions are called domains. The SH7786 Group employs EXREAL-ExARIA, a communication interface (domain interoperation) technology for integrating the OS of multiple domains, and EXREAL-ExVisor, a technology for preventing interference between the operating systems of multiple domains. These two technologies help simplify the development of distributed function systems using multicore devices. They make it possible to use existing software resources originally developed for use with a single SH-4A CPU core in systems built around a SH7786 Group dual-core processor, thus shortening the time needed for development. They also make it possible to run multiple OS with a high level of reliability.

The SH7786 Group dual-core processor includes User Debug Interface (H-UDI) and Advanced User Debugger (AUD) on-chip debugging functions. They support realtime debug and trace at the processor's maximum operating frequency. Additional products such as emulators enable flexible debugging and ease the burden of software development for the customer.

The SH7786 Group implements multiple PCIe bus interfaces that can be set to operate as one to four lanes, enabling high-speed data transfer at up to 800MBps.

Samples of the first product version, fabricated at 90nm, are currently being shipped to selected automotive customers. The second product version, fabricated using a 65nm process, is under development. The 65nm version will provide reduced power consumption and an enhanced cost to performance ratio.

Sample shipments in Japan will begin in October. The device will be made available to Renesas Technology's wide base of consumer and industrial customers in 2009.




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