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Low-power 32Mbit, 64Mbit SRAMs roll

Posted: 28 Mar 2008 ?? ?Print Version ?Bookmark and Share

Keywords:low-power SRAM? Advanced LPSRAM? pseudo SRAM? stacked capacitor memory cell?

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Renesas Technology Corp. has introduced the R1WV6416R Series of 64Mbit Advanced Low-Power SRAM (Advanced LPSRAM) products with the highest LPSRAM capacity currently available, and the R1LV3216R Series of 32Mbit Advanced LPSRAM products with compact chip size.

The R1WV6416R Series of 64Mbit Advanced LPSRAM products and the R1LV3216R Series of 32Mbit Advanced LPSRAM products are available with access times of 55ns or 70ns, and in TSOP I (48-pin), ?TSOP (52-pin), or (for 64Mbit products) FBGA (48-ball) packages. The package of the TSOP I (48-pin) products is identical to that of current 16Mbit products, and the package of the ?TSOP (52-pin) is identical to that of current 8Mbit, 16Mbit and 32Mbit products. FBGA (48-ball) products have a ball layout that is backward compatible with that of current 4Mbit, 8Mbit, 16Mbit and 32Mbit products. This enables customers to increase memory capacity while continuing to use their existing layout designs.

Main features
The 64Mbit low-power SRAM products each comprise a stack of two compact 32Mbit Advanced LPSRAM chips in a single package, resulting in the highest capacity in the industry. They meet demand for larger-capacity low-power SRAM for high-performance systems and meet reduced space requirements in applications that previously would have required multiple low-power SRAM devices.

To accommodate a variety of applications, these two new series are being offered in several different packages: TSOP I (48-pin), TSOP (52-pin), and for 64Mbit products FBGA (48-ball). The TSOP I and ?TSOP packages have the same dimensions as those of previous 16Mbit products, and the ball layout of the FBGA package is signal pin compatible. This enables customers to increase memory capacity while continuing to use their existing layout designs.

Advanced LPSRAM uses a stacked capacitor memory cell configuration, an approach with a proven track record in DRAM cells. It virtually eliminates soft errors caused by alpha radiation or high-energy neutron radiation, which can be a problem with ultrafine SRAM. In addition, this memory cell configuration avoids the unintended formation of an parasitic thyristor, which can generate spurious current flows and cause latchups. Elimination of soft errors and latchups provides excellent reliability.

Small chip size
According to Renesas, Advanced LPSRAM eliminates soft errors through the use of stacked capacitors and reduces the surface area of each memory cell by employing a vertical configuration in which the stacked capacitors are formed in a layer above the transistors. The SRAM cells use polysilicon TFTs as P-channel load transistors. By forming these in a layer above the other transistors and reducing the number of transistors underneath, the memory cell surface area is reduced. Says renesas, this is the reason the 32Mbit R1LV3216R Series has the smallest chip size in the industry for a 32Mbit low-power SRAM product.

In addition, the transistors underneath comprise driver and access transistors with an N-channel only, so there is no danger of a parasitic thyristor configuration being formed in the memory region and latchups cannot occur in theory. Elimination of soft errors and latchups provides excellent reliability.

Advanced LPSRAM also requires no refreshes and thus, uses less power than pseudo SRAM, which uses SDRAM or DRAM memory cells as the SRAM interface. This makes it suitable for low-power applications that use batteries for data backup.

Sample shipments in Japan of the 32Mbit products will begin in April. The 64Mbit products will start sampling in July.





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