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MIPS unveils licensable core for multiprocessing

Posted: 03 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:MIPS licensable core? multiprocessing? multicore designs?

MIPS Technologies Inc. is rolling out at this week's Multicore Expo its first licensable core geared for coherent multiprocessing. The MIPS 1004K can support up to four cores on a chip, each running two threads.

A dual-core 1004K delivers 2,400 Dhrystone MIPS (DMIPS) running at 800MHz, besting the company's high end single-core 74K chip which delivers 2,000DMIPS. The core will ship as RTL code starting in June.

"This is the first time we have used multiple cores to get to higher performance levels," said Jack Browne, VP of marketing for the company's processor group.

ARM's multicore efforts
Archrival ARM Ltd demonstrated its first multicore implementation, the ARM 11 MPCore, in July 2005 and followed it up with a multicore version of its Cortex-A9 launched last October. ARM has chosen so far not to support multithreading.

"In some applications we can get 35 percent better performance with multithreading on the 1004K, so we think its worth it, and we have had three years of good experience with multithreading" on the MIPS 34K core, Browne said.

Multithreading support requires less than 10 percent more silicon area at the core level, and an even smaller percentage at the SoC level, he added.

ARM believes multithreading delivers only marginal performance increases, said John Goodacre, multiprocessing program manager at ARM. In addition, the technology can slow throughput and single-thread performance as well as introduce extra software complexity, he added.

MIPS claimed its dual-threaded, single-core 34K delivers 1.6DMIPS per MHz compared to 1.4DMIPS for the ARM 11. However, Goodacre said the latest Cortex-A9 can hit 2.5DMIPS/MHz.

Browne of MIPS said it's too early to have performance data to compare the two companies' latest processors. "Both of us are taking our different architectures and using similar techniques to make them multicore," he said.

Multithreading benefits
"In general there is a significant benefit for multithreading," said Linley Gwennap, principal of The Linley Group. "The benefits of multithreading depend on the applications and the CPU design, but the point is to make up for lost cycles when a core stalls," he said.

MIPS is shipping several silicon blocks along with the 1004K, aimed at managing a multicore design. A coherency manager block is required for multicore chips. Two optional blocks are a global interrupt controller that can help optimize a multicore design and a peripheral block to increase I/O efficiency up to 25 percent.

"I expect most initial designs will use two cores at 65nm," said Browne. "I expect we will start seeing four cores used when people move to 45nm technology," he added.

The chips are geared for a wide range of high-end consumer and communications systems. They include STBs built for managing multiple digital recording streams and VoIP, residential gateways supporting multiple home networking types and high-speed PON connections and Blu-ray optical drives supporting interactivity and Web access.

Linux support
MIPS has been helping develop a symmetric multiprocessing version of Linux for the new core. It should be ready when the RTL for the core ships in June.

RTOS support will probably lag until the core gets market traction. The 34K multithreaded core, which shipped in 2006, is now supported by Nucleus, ThreadX and MontaVista Linux.

So far, MIPS has garnered about 10 licensees for its multithreaded 34K core. The 1004K has shipped in an alpha release version to one customer.

Goodacre said ARM has 14 licensees for its ARM11 MPCore, including Intel, NEC, Nvidia, PMC-Sierra, LSI and Renesas. Its Cortex-A9 MPCore has eight licensees including NXP, Samsung, STMicro and Texas Instruments.

MIPS does not face a time-to-market penalty with the 1004K introduction, said Gwennap.

"There are a lot of embedded multicore processors out there but not that many licensable multiprocessing cores," said Gwennap. "This helps people design multicore chips quickly without needing to develop the underlying logic," he added.

- Rick Merritt
EE Times





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