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Implementing DDR2 PCB layout on the TMS320DM646x (Rev. A)

Posted: 25 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:TMS320DM646x DSP? DDR2 PCB layout?

This document from Texas Instruments contains implementation instructions for the DDR2 memory controller interface contained in the TMS320DM646x DSP devices. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices.

The previous approach specified device timing in terms of data sheet specifications and simulation models. The customer was required to obtain compatible memory devices, as well as their data sheets and simulation models. The customer would then take this information and design their PCB using high-speed simulation to close system timing.

For the DM646x DDR2 interface, the approach is to specify compatible DDR2 devices and provide the PCB routing rule solution directly to the customer. TI has performed the simulation and system design work to ensure DDR2 interface timings are met. The DDR2 system solution is referred to as the DM646x DDR2 collateral.

The DM646x EVM provides an example PCB layouts following these routing rules that passes FCC EMI requirements. The DDR2 layout on the EVM meets the routing rules detailed in this document. The customer may copy the DDR2 layouts directly, but the intent is to allow enough flexibility in the routing rules to meet other PCB requirements and allow the customer to derive an optimized layout for their specific application.

View the PDF document for more information.





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