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Partition and package to miniaturize handsets

Posted: 01 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:3D IC stacking? system-in-package? wafer-level packaging?

The latest generation of mobile phone handsets and smart phone/PDAs has replaced the PC as the advanced technology driver for the electronics industry. The sheer volume alone is amazing, but the underlying story is the advanced technology that makes this increased volume possible. To meet changing form factors and performance requirements for next-generation devices, designers are leveraging some of the most advanced semiconductor technologies available for IC content, as well as advanced packaging and interconnect technologies.

The typical smart phone features a host of ICs ranging from microwave RF, memory and power management ICs to DSPs and reprogrammable host processors. New devices feature image sensors and image processors, audio processors, MP3 devices, display drivers, LED drivers, and image displays.

Given the number of ICs in a modern handset, placing them on PCBs and routing them to be properly interconnected in a tight layout is a daunting task. Accommodating its functions and achieving the requirements of the semiconductor device technology needed to efficiently implement these functions require full integration that is not entirely possible today. To hurdle this roadblock, designers are turning to system-in-package (SiP), 3D IC stacking and wafer-level packaging (WLP) to enable the acute miniaturization found in handsets, particularly for RF functions.

RF partitioning
Perhaps the most difficult task in dealing with RF functions is engineering all radio systems to work properly and without interference when placing them in close physical proximity in shrinking handset form factors. Testing, packaging and reliability pose significant challenges when designing for RF.

The variety of active and passive components required to build a cellular radio makes single-chip integration impractical. A more efficient approach is to partition each RF subsystem into a multichip module or SiP. This simplifies handset assembly because there is no need to individually test and tweak each radio: All of them represent finished subsystems at the time of handset PCB assembly.

SiPs are developed in several ways. One way is to place discrete capacitors and resistors on a laminate substrate and then make spiral inductors from signal routing traces. The semiconductors may then be individually packaged, flip-chipped or wire-bonded to the substrate. In some cases, they may be stacked in die form by using wire-bonding or flip-chip connections or a combination of both. Substrate materials used may include FR4, BT buildup structures and other such laminates.

In another approach, die-stacking technology is used in GPS receiver SiPs to reduce footprints. For transceiver SiPs, receiver ICs are separated from transmitter ICs to improve isolation, increasing the effective footprint of the SiP. By embedding the capacitors and resistors into the SiP substrate, passive components can be placed under the ICs to reduce the SiP footprint. Electrical performance is improved by minimizing the influence of parasitic elements. Thin, coreless buildup substrates can be deployed to further shrink physical dimensions, thereby reducing undesirable parasitic loading while minimizing the vertical height of the module.

Unfortunately, microwave RF IC die testing is affected by the loading of probe needles, bondwires and sockets. When probed in wafer form, the die doesn't have the same load circuit that it will see in the handset. Likewise, when the die is attached to an SiP using bondwires, the loading will change so it is unlike the bare die. Even a packaged die placed in a socket will experience the loading of the socket contactor. Such variations can require some retuning of the RF SiP.

New technologies are being developed to allow the die to be fully tested without the use of a conventional socket. For instance, Tessera's PILR technology is composed of a thin substrate combined with etched copper posts plated with nickel/gold for external connections. Because the posts are etched from a rolled sheet of copper, they are highly coplanar, which, combined with the compliant material, permits contactor-less sockets to be used in component testing.

Because the nickel/gold-plated copper posts directly make contact with the PCB without socket contactors, the device behaves the same in testing as it does in the final circuit. This can significantly reduce the need for expensive reworking and tuning of the finished SiP or handset. At the same time, using the etched posts allows designers to adjust the pitch to hit significantly finer levels than are possible with traditional solder balls, permitting chip-sized footprints for SiP modules.

Stacking solutions
Another approach to realize small form-factor requirements is 3D IC stacking. Digital processors such as baseband and host processors are often stacked with memory in a package-on-package (PoP) configuration. This saves IC footprint space on the PCB and can increase signal routing density while greatly reducing routing that otherwise would need to be done on the PCB. From a handset manufacturer's perspective, PoP stacking also provides a simple way to change the feature set in the handset, as a range of processors and memory can be configured to share a common PCB footprint.

Wafer level packaging (WLP) is another option. Memory dice are often stacked and packaged as multichip units. Each die stack is interconnected to package leads using wire bonds to the individual die in the stack, which can be expensive. WLP offers a cost-effective alternative with higher-density capacity. A second method uses through-wafer vias for device interconnection. Both methods provide extremely dense memory stacks of vertical stacking at a 30?m pitch while eliminating slow throughput and rework issues associated with wire-bonding as the dice are bonded while in wafer form.

Camera modules also benefit from stacking. Camera modules occupy significant real estate within mobile handsets, presenting a challenge as phone devices continue to scale down to smaller sizes and profiles. WLP enables greater integration at the wafer level, reducing overall size and cost, while still providing scalability for next-generation handset design and development. Size is reduced by leveraging WLP to manufacture thousands of lenses simultaneously on a wafer, with alignment and bonding accomplished at the wafer level to create the camera's optical element. This eliminates the need for manual focusing of the camera module during manufacture, and it cuts costs.

As traditional packaging technologies using solder balls move to finer pitches, reliability becomes more challenging. Smaller solder ball pitches mean smaller wetted surface areas per connection, which in turn, concentrates mechanical stress into smaller areas than would be the case using larger solder balls with looser pitches.

Smaller solder balls also have less resilience than larger solder balls, which means they can simply flex or deflect more pitches without failure. Drops and thermal cycling introduce mechanical stresses to solder joints. Solder joints can crack unless the package/solder combination has been properly engineered.

Common solutions for conventional chipscale packages include the use of underfill below SMDs. However, finer pitches make it harder to inject the underfill material: Its viscosity makes it simply more difficult to get the material to flow between the solder balls on the package when fine-pitch solder connections are used.

An alternative approach, using chip scale packages (CSPs) employs a compliant die-attach adhesive layer used within the package. The compliant layer absorbs mechanical strain to assure reliability.

Advanced packaging and interconnect methods meet miniaturization requirements.

In the PoP method, components are stacked after die packaging, permitting the final component configuration selection to be made late in the process. Depending on the type of package used, PoP stacks may be significantly thicker and have much greater mass than bare die stacks. For example, standard plastic over-molded BGA-packaged chips may be impractical for stacking higher than two levels in a handset because of thickness and mass/shock constraints.

More advanced stacked packages using posts rather than solder balls provide thinner profiles and lower mass for PoP stacking. The posts provide the desired standoff heights for a particular design, helping to shrink the form factor. They also provide a greater wetted surface area for better solder adhesion.

Cost reduction
The BOM and the assembly costs affect final handset costs. Extensive use of high-integration SiPs, PoPs and CSP helps minimize assembly time, thus reducing cost. Additionally, PCB area and routing layers may be minimized when using stacks and SiPs because of the reduced number of components and signals routed in the PCB. Saving area and routing layers in the system PCB reduces BOM cost. Meanwhile, reducing component piece part count reduces assembly costs and increases yield.

Moreover, using common footprints for the SiPs and processor/memory stacks can provide an easy way for the handset manufacturer to make families of similar but functionally differentiated products by using a simple build-time BOM option scheme: A different kit of parts is used for different feature sets, with all of them using the same system PCBs and cases.

Mobile handsets require the latest semiconductors and packaging technology to meet increasingly challenging size and functionality demands as well as strict manufacturing cost and reliability requirements. Because of the diverse technologies needed to accomplish these circuit functions, full integration is unlikely for the foreseeable future. Research is ongoing for the next technology breakthrough. In the meantime, to continue the Moore's Law trend toward smaller, sleeker handset devices, designers can leverage advanced packaging and interconnect various methods to meet miniaturization requirements.

- Richard Crisp
Director, High-Performance Packaging
Tessera Inc.





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