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Designing DSP-based digital DC/DC power supply (Part 2)

Posted: 05 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DC/DC? power supply? digital controller? ADC?

By Shamim Choudhury
Texas Instruments Inc.

As discussed in Part 1 in this tutorial, while the design by emulation method allows the power supply designer to do the control design in the familiar s-domain and then convert it to a discrete/digital controller, the second approach, described here, direct digital design, allows design directly in z-domain without conversion.

The first step is to redraw Figure 1 from Part 1 as in Figure 6 to show all the different components of this closed loop control system including the effect of sampling and hold.

Figure 6: DC/DC converter digital control loop block diagram

In this approach, the sampling process by the on-chip ADC is represented by an ideal sampler with time period Ts. ADC can be represented this way as compared to the model given in [7], since the ADC gain is taken into account in the block labeled Kd and ADC conversion time is included in the computation delay block labeled Hc. The on-chip pulse-width modulation (PWM) module acts as a hold device.

Representing this as a zero-order-hold (ZOH), the ADC and the PWM module together form a sampling and hold device. The effect of such sample and hold action is to introduce a time delay of Ts/2 or a phase lag of (omega)Ts/2 as illustrated in Figure 7. Here a signal is sampled at time interval of Ts and then reconstructed through ZOH. The reconstructed signal is found to lag the original signal by (omega)Ts/2 radian or 180f/fs degree.

Figure 7: Sample and hold process in a digital system

The s-domain transfer function [9] of such a device can be expressed as,

Thus we see that the effect of the sampling and hold process in a digitally controlled power supply is that it introduces an additional phase delay of 180f/fs degree compared to an equivalent analog controlled power supply. Here, f is the frequency of interest, i.e. the bandwidth, where the phase is calculated.

So, for the Bode plot shown in Figure 4 in Part 1, where we ignored the effect of sampling and hold, the actual phase margin is at least reduced by 18 degree (=180x25kHz/250kHz). This means that this system can have a PM of at most 53 degree (=71-18). In reality this will be further reduced by the computation delay associated with any digital system. This explains the reason for the under-damped response of this system as shown in Figure 5 in Part 1.

The computation delay block Hc, models the time delay between the ADC sampling instant and the subsequent PWM duty ratio update. This time delay is denoted by Td and the transfer function for Hc is,

In direct digital design approach, the continuous time power stage model is first discretized with ZOH and the sampler. Once this is available, the discrete-time compensator. i.e., a digital controller Gc(z) is designed directly in the z-domain using methods similar to the continuous-time frequency response methods.

This has the advantage that the poles and zeros of the digital controllers are located directly, resulting in a better load transient response, as well as better phase margin and bandwidth for the closed loop power converter. The discrete-time transfer function Gp(z) of the converter plant, including the ZOH, the sampler, the voltage sensing gain Kd and the computation delay [9] model Hc is,

where, Z denotes the z-transform of the function inside the parenthesis {}. This can be computed in MATLAB by writing the MATLAB script as:

Vin=5.0; Vo=1.6; Io=16; Kd=0.5; L=1e-6; C=1620e-6; Rc=4e-3; RL=Vo/Io; Ts=4.0e-6; Td=0.0*Ts; num_Gps=Vin*[Rc*C 1]; denom_Gps=[L*C*(1+Rc/RL) (L/RL+Rc*C) 1]; Gps_dly=tf(num_Gps,denom_Gps,'inputdelay',Td); %s-domain plant with computation delay Td%Gpz=c2d(Gps_dly*Kd,Ts,'zoh'); %Discrete plant with ZOH, Kd and Td%

The resulting discrete plant obtained from MATLAB is,

Where Kd = 1/Vomax = ?, Ts = 1/fs = 4 microsecons and the computation delay Td, for now, is taken as Td = 0, i.e., Hc = 1.

Figure 8: DC/DC converter digital control loop Bode plot Gp1*Gc2 (MATLAB)

For this plant GP1, a suitable digital controller is designed in MATLAB using the 'sisotool'. The system bandwidth is set at 27.9 kHz with a phase margin of 61.6 deg. The Bode plot is shown in Figure 8. The corresponding controller GC2 is derived from MATLAB as,

In discrete form, this controller is written as,

U(n) = 1.473U(n -1) - 0.4731U(n -2) +14.87E(n) - 26.91E(n -1) +12.16E(n -2)

This controller was implemented using the TMS320F280x DSP instruction set.. The fixed point format used for these controller coefficients is Q26.


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