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DDR3 dynamic on-die termination

Posted: 12 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DDR3? SDRAM? on-die termination?

DDR3 SDRAM technology has the ability to transfer data at a much higher rate than previously possible. With these improved data rates, designers need options to improve the signal integrity of the data bus, while still maintaining performance. This technical note will describe dynamic on-die termination (ODT), which is a new feature introduced with DDR3 and provides systems with increased flexibility to optimize termination values for different loading conditions.

For optimum signaling, a typical dual-slot system will have a module terminate to a LOW impedance value (30? or 40?) when in an idle condition. When the module is being accessed during a write operation, greater termination impedance is desired, for example, 60? or 120?. Dynamic ODT enables the DRAM to switch between high or low termination impedance without issuing a mode register set command. This is advantageous because it improves bus scheduling and decreases bus idle time.

View the PDF document for more information.





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