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Memory/Storage??

Memory IP zooms in on OTP apps

Posted: 27 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:memory? IP? apps OTP SLP?

Sidense, a developer of Logic Non-Volatile Memory (LNVM) IP cores, announced the Sidense Low Power (SLP) one-time programmable (OTP) memory macrocells for low power and cost-sensitive applications that require highly secure information storage.

Applications include secure key storage, implantable medical devices, RFID, handheld wireless communication devices, analog trimming, and power and energy management.

Based on Sidense's patented split-channel architecture, SLP memory macro implementation requires no additional masks or process steps, thus adding no extra wafer processing cost. Implemented at 180nm, SLP macros are available in densities up to 256Kbit and multiple blocks may be stitched together for larger memory capacity. Power dissipation is very low, up to 80 percent lower power compared to competitive products, according to the company.

Typical read current for a 256Kbit macro is 0.25?A/MHz/bit with a 2.5V read voltage. Macro sizes are also very small a 256Kbit memory takes less than 0.5mm ? of silicon.

Sidense OTP memory is available at 180nm, 130nm, 90nm and 65nm and scalable to 45nm and below. The IP is available at UMC, TSMC, SMIC, Tower and Chartered. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, RFID and chip ID, medical, automotive, and configurable processors and logic.

- Ismini Scouras
eeProductCenter





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