Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > T&M
?
?
T&M??

Toshiba develops cost-competitive MEMS

Posted: 03 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:micro electro-mechanical systems? MEMS packaging? hermetic cavity packaging?

Toshiba Corp. has announced two optimized packaging technologies for micro electro-mechanical systems (MEMS) semiconductor packages that achieve significant cost reductions.

The first technology covers encapsulation under normal atmospheric condition, the second a stronger structure for vacuum sealing. Both technologies can be applied at the wafer level, and both have been used to achieve multi-chip MEMS packaging with a control IC at a thickness of only 0.8mm, the thinnest yet announced, according to Toshiba. Both achievements were reported last week at the Electronic Components and Technology Conference 2008.

As achieving cost efficiency and high productivity is one of the key objectives of MEMS, there are significant demands for small sized, hermetic cavity packaging technologies. Vacuum sealing is utilized in high-speed applications, such as MEMS switch and gyroscopes, but there are various problems with this, including ringing. In applications where high speed is not required, such as use in mobile phones, low cost encapsulation under normal atmospheric condition technology is employed. Toshiba has developed both packaging technologies.

Development
In the encapsulation under normal atmospheric condition, a hermetic cavity is formed by coating a polymer sacrifice layer with SiO2 film, etching a cavity on the sacrifice layer through holes driven through the film, and then covering the film layer with a polymer cap. Etching efficiency is increased with larger holes, but this also raises the danger of polymer inflow into the cavity. Toshiba overcame this challenge by optimizing hole size and shape, achieving increased production efficiency and preventing any inflow.

Moreover, previous applications of this technology to MEMS chips was limited to non-water-resistant covering materials, but Toshiba also achieved a moisture-resistant package through chemical vapor deposition (CVD) of a hybrid structure organic and inorganic films.

In vacuum sealing, air pressure on the hermetic cavity can cause chip failure. Toshiba overcame this with application of a new corrugated encapsulation structure that increases pressure resistance.

In addition, changing the shape of the etching holes from circles to ovals reduced stress and risk of damage during etching. In a further step, laminating a thicker layer extended the process to multiple level cell packaging, where high pressure resistance is essential.





Article Comments - Toshiba develops cost-competitive ME...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top