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Implement an FPGA ASIC prototype

Posted: 16 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:ASIC? FPGA for digital electronics design? functional verification?

Over the past decade, designers around the world have argued the relative merits of using ASICs vs. FPGAs to implement digital electronic designs. This discussion has typically positioned the performance advantages and low power consumption of fully customized ICs against the flexibility and low NRE costs of FPGAs.

Should a design team make the upfront NRE investment in an ASIC design to maximize performance, reduce footprint and drive down costs at high volumes? Or is the design team building an end product for a market that demands the highly configurable feature sets and quick turnaround that only FPGAs can provide?

Verification value
Surprisingly, the escalating challenges of high-density IC design are, in many ways, making that argument irrelevant. As ASIC designers migrate to each new process node, designs grow increasingly complex, software content rises and verification runtimes lengthen. Moreover, recent research indicates that more than 60 percent of respun ASICs fail not because of timing or power issues, but because of logical or functional errors. For this reason, functional verification has become the single most critical phase of the ASIC development cycle and often the most time-consuming.

An increasing number of ASIC designers find that they can best meet their requirements by prototyping the functional equivalents of their designs as FPGAs. In fact, more than 90 percent of all ASICs today are either partially or completely prototyped as FPGAs before tape-out. Thus, the question is no longer whether to implement an IC design as an ASIC or as an FPGA. To meet the demands of today's markets, most design teams must do both.

Given the critical need for first-pass silicon and the escalating possibilities for bugs as ASIC densities climb and design complexities increase, designers need a verification methodology that can find all bugs in a reasonably short time. Traditional software simulation techniques can no longer support design teams who are racing to squeeze into tight time-to-market windows.

Consider a typical mobile phone chipset design. RTL simulation offers a high level of visibility into the design. However, the low performance associated with software simulation means that booting the phone chipset could take as long as 30 days, making the process unfeasible and significantly limiting the level and amount of verification possible. HW/SW co-simulation approaches that use higher-level models can reduce the time required for the OS boot to 10 days, but even that is still not very useful. Moreover, these approaches require the development of complex testbenches, which, by their very nature, are incomplete. Meanwhile, C model simulation offers shorter runtimes perhaps as short as 24hrsbut can't deliver the level of detail that ASIC designers typically require.

FPGA prototype wins
ASIC designers need a verification strategy that offers speeds approaching that of the ASIC. They need a methodology to leverage real-world stimulus, not a testbench. They need a highly affordable and easily deployable verification methodology to support distribution for hardware and software debug within the whole design team. Moreover, they need a verification strategy that can run OS and application software at speed, and easily integrate external system components and interfaces.

By implementing an ASIC prototype as an FPGA, designers can run millions of test vectors per seconda process roughly 1 million times speedier than traditional software simulation. A mobile phone chipset that might spend up to a month in a software simulator runs in as little as 30s as an FPGA prototype.

That performance advantage offers enormous benefits during the software and system integration stages of the design cycle. By running at speeds approaching the ASIC itself, an FPGA prototype allows designers to verify embedded or application software against their hardware; stream video or networking data to test performance and identify hard-to-find bugs; and, if the design incorporates embedded CPUs, verify an OS performance before the ASIC design is complete. Moreover, by applying real-world stimulus to the design, verification engineers can eliminate the time-consuming task of testbench development.

Tool considerations
Perhaps the biggest question for ASIC designers is not whether to prototype their designs in FPGAs but, rather, what types of capabilities they should look for in an ASIC-to-FPGA conversion tool.

Few designers have the time or resources to implement their IC as both an ASIC and an FPGA. Distinct differences separate not only the technologies themselves, but also their use. Thus, if an ASIC prototype platform is to succeed, it must first be able to accurately translate the architectural distinctions separating ASICs and FPGAs.

Partitioning is a second necessary function of an ASIC-to-FPGA tool. As ASICs have grown increasingly complex, integrating a wider array of functions, designers seeking to verify their designs rapidly and cost-effectively have had to partition their chips' functionalities across several FPGAs. Many ASIC designers opt to perform this task by hand an error-prone and inherently risky process.

Verification engineers must also ask how the ASIC prototyping tool allows users to measure and tweak performance once the design is ready for synthesis. Does the tool let users optimize timing paths? Does that ability extend to those paths crossing multiple FPGAs? Does the tool provide any reports or analysis on timing performance that users can evaluate with the prototype before the actual programming of the hardware?

By using FPGAs as a prototyping platform to gain insight into and verify an ASIC' s functionality, designers can quickly and affordably identify potential bugs, reducing the overall risk associated with products while meeting time-to-market deadlines.

- Juergen Jaeger
Senior Director
ASIC Verification Marketing
Synplicity Inc.





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