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UMC tips roadmap, veers away from 450mm

Posted: 16 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:foundry service? UMC roadmap? 450mm?

Taiwan foundry United Microelectronics Corp. has outlined its process roadmap and disclosed several alliances with the EDA community at the Design Automation Conference (DAC).

UMC also disclosed that unlike its foundry rival in the island, it is not pushing the next-generation 450mm wafer size.

The second largest foundry has been ramping up 65nm processes for some time but it will shortly move into the 45nm and 40nm nodes. Like its foundry rivals, the company has pushed out its high-k and metal gate solution to the 32nm node.

As of late, the company has been somewhat less vocal about its cutting-edge process technologies, as compared to IBM's "fab club" and Taiwan Semiconductor Manufacturing Co. Ltd. "We're definitely not behind," said Lee Chung, VP of the corporate marketing division at UMC.

40-/45nm nodes
Like TSMCand reportedly Chartered Semiconductor Manufacturing Pte LtdUMC is developing a 45nm process and will also provide a 40nm "half-step" technology.

UMC's 45-/40nm process is multi-level metal technology with copper interconnects and ultra low-k dielectrics. At that node, UMC's low-k technology will have a "k effective" value of 2.5, compared to 3.0 at 65nm.

The company will also make use of immersion lithography at those nodes. Its 45-/40nm processes are expected to move into initial production by year's end, Chung told EE Times at DAC.

UMC is also working on its 32nm process, which is expected to be released at the end of 2010. The process will make use of high-k and metal gates, but the company declined to elaborate on the technology.

The foundry is expected to ramp up its 45-/40nm technology in Fab 12, a 300mm plant located in the southern Taiwan city of Tainan.

No to 450nm
At least for now, UMC is not pushing for 450mm fabs. In contrast, rival TSMC, as well as Intel and Samsung are pushing the industry towards 450mm fabs, which are being targeted for the 2012 time frame.

"Today, 450mm is not exciting," Chung said. "At 300mm, there are so many [productivity improvements] you can do."

Asked if he saw 450mm fabs appearing in 2012, he said: "I don't believe it." The real problem is the equipment makers, which "are not excited" about moving towards the next-generation wafer size, he said.

EDA alliance
Meanwhile, at DAC, UMC announced a number of alliances with EDA houses. Cadence Design Systems Inc. and UMC announced the availability of a Common Power Format -based low-power reference design flow targeted to UMC's 65nm process.

Synopsys Inc. and UMC, too, announced the release of a low-power design reference flow supporting the foundry's 65nm technology. The new reference design flow includes RTL-to-GDSII design capabilities based on the Unified Power Format (UPF) standard.

Magma Design Automation Inc. and UMC announced the availability of a validated UPF-compliant low-power RTL-to-GDSII design flow that uses the UMC's 65nm library. And not to be outdone, Extreme DA and UMC announced their collaboration on variation-aware IC design flows for 65nm and finer process technologies.

- Mark LaPedus
EE Times





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