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DesignWare IP packs fully synthesizable PowerPC cores

Posted: 25 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:PowerPC core? multicore processor? IP portfolio?

Synopsys Inc. has included fully synthesizable IBM PowerPC 460 and cache configurable PowerPC 405 embedded microprocessor cores in its DesignWare Star IP program.

The PowerPC 460S is a 32bit high performance, low-power embedded processor core optimized to meet the performance and power requirements of consumer electronics, communications and storage applications. As a synthesizable version of IBM's PowerPC 464 hard core, the PowerPC 460S allows the SoC designer to select the L2 cache size, L1 cache size and multicore processor local bus necessary to optimize their design. Additionally, the PowerPC 460S supports an optional floating point unit.

Meanwhile, the PowerPC 405S is a 32bit low-power, mid-performance embedded processor core with design attributes that make it a suitable solution for emerging consumer, storage, wired and wireless applications. As a synthesizable version of IBM's hard core series, the PowerPC 405S now supports a user-definable L1 cache size that helps SoC designers optimize performance and area to match the application requirements.

"These new synthesizable versions of the PowerPC 460S and 405S embedded cores take advantage of Synopsys' expertise in IP design, delivery and support to ease customers' integration effort," said Ron Soicher, VP of alliance strategy, IBM systems and technology group. "The combination of process portability and compatibility with standard synthesis-based design flows reduces major cost and design barriers, and make the Power Architecture more readily available to all SoC designers."

Developed through a close collaboration between IBM and the Synopsys Professional Services and DesignWare IP teams, the foundry-independent processor cores are supported by a broad range of design tools in the Synopsys Galaxy Design and Discovery Verification platforms. The PowerPC 460S and 405S processors are distributed as simulation and timing models and synthesizable RTL cores. Synthesizable IBM CoreConnect peripherals are also available to licensees of the PowerPC cores. The combination of synthesizable PowerPC cores and CoreConnect peripherals with the DesignWare IP portfolio gives designers a comprehensive PowerPC solution spanning all facets of SoC design from system-level design to implementation.

"The addition of these new cores to our DesignWare Star IP portfolio highlights the success of our multi-year collaboration with IBM to deliver products that support the Power Architecture," said John Koeter, senior director for IP and services at Synopsys. "These new cores offer designers a low-risk path to silicon with the flexibility to implement designs in their choice of process technologies."

Synopsys' distribution of the PowerPC cores supports the goals of Power.org by providing designers around the world with access to the Power Architecture and with a means to implement it in their preferred process technology.

PowerPC 460S and PowerPC 405S design views, including the simulation and timing models, a verification environment, and full documentation are currently available at no additional charge to DesignWare Library customers. For an additional fee, DesignWare Library users may license from IBM or Synopsys the implementation views of the core, including fully synthesizable RTL.





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