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eASIC jumps to 45nm, finds new foundry partner

Posted: 06 Aug 2008 ?? ?Print Version ?Bookmark and Share

Keywords:foundry partner? 65nm node? 45nm process? photomask?

Fabless vendor eASIC Corp. will skip the 65nm node and roll out what it calls a "zero mask charge" 45nm ASIC line.

In addition to launching the Nextreme-2 family, the fabless supplier of structured ASICs has switched foundry partners, from Japan's Fujitsu Ltd to Singapore's Chartered Semiconductor Manufacturing Pte Ltd.

Fujitsu processes eASIC's 90nm structured ASIC devices using direct-write electron-beam technology from e-Shuttle Inc., a joint venture between Fujitsu and Advantest Corp. By contrast, eASIC's 45nm parts will be manufactured using 193nm immersion lithography.

Ronnie Vasishta, CEO of eASIC, said the company will continue to sell the 90nm ASICs and that Fujitsu will continue to manufacture them. The fabless company, he said, was "very, very happy with Fujitsu" but wanted to accelerate its efforts in the 45nm process race, in which analysts say Fujitsu is lagging.

The unexpected availability of 45nm process technology in the market made the company decide to skip the 65nm manufacturing node, Vasishta said, noting that the 45nm node gives ASICs some innate advantages over rival FPGAs and ASSPs.

In general, FPGAs are limited in terms of their overall architecture, while ASSPs have some limitations in their customization, he said. Thus, 45nm ASICs will provide "increased functionality" at "better performance" for customers.

40-/45nm ramp up
Competitors are likewise gearing up for the 45-/40nm node. IBM Corp. has already announced a 45nm ASIC line, while Altera Corp. recently rolled out a separate FPGA and structured-ASIC portfolio based on 40nm technology from Taiwan Semiconductor Manufacturing Co. Ltd.

Other fabless ASIC houses, including eSilicon Corp. and Global Unichip Corp., are developing 45- or 40nm ASICs. Taiwan's Global Unichip claims it will have a 32nm test device by year's end. Both eSilicon and Global Unichip exclusively use TSMC as their foundry.

In total, the ASIC market is expected to grow a mere 3.7 percent in 2008, according to Gartner Inc. Only 2 percent of worldwide ASIC tape-outs this year will involve 45-/40nm technologies, but the leading-edge market is growing, the research firm believes.

"Demand for 45nm ASIC designs is starting to pick up, but it is primarily top-tier ASIC vendors working with large system companies that can afford the higher costs of leading-edge ASICs," said Bryan Lewis, an analyst with Gartner.

Soaring IC design costs and photomask prices have put ASICs out of reach for many smaller customers. IC design costs, which now range between $20 million and $50 million, are expected to average about $75 million at the 32nm node.

With a new twist in the structured-ASIC model, eASIC "is trying to lower the barriers to entry, so smaller [customer] companies can get the benefits of leading-edge ASIC technology," Lewis said.

Founded in 1999, eASIC recently raised a whopping $48 million in late-stage financing. The March funding round brought the company's total capitalization to $80 million.

The fabless chip house began to gain traction in a crowded market starting at the 90nm node. It claims to have about 120 design wins for its older-generation devices in the consumer, military and wireless markets.

At 90nm, eASIC preprocesses wafers up to the so-called Metal-6 layer. When a customer places an order, the Metal-6 layer is processed via direct-write e-beam at eShuttle, thereby supposedly eliminating nonrecurring engineering costs.

Optical lithography
The Nextreme-2 line will be manufactured on Chartered's 45nm low-power process. Instead of e-beam, Chartered uses 193nm immersion optical lithography. At the foundry, eASIC will maintain an inventory of preprocessed wafers up to the so-called Via-4 layer, processing it only when a customer places an order.

Vasishta said eASIC will make use of Chartered's multiproject wafer technology to ensure there are no mask charges. Multiproject wafers assemble several devices from multiple vendors on one photomask, thereby lowering and amortizing mask costs over time.

Despite the move to optical lithography, the company claims it can still deliver working devices in only six weeks. The 45nm lineup comprises the Nextreme-2 and Nextreme-2T families.

The Nextreme-2 series includes six ASIC lines, ranging from 2,700 K to 19,900 K logic cells. The logic fabric within the devices is said to provide up to 700MHz of performance.

The Nextreme-2T line consists of two devices, at 10,500 K and 19,900 K logic cells. The line includes a transceiver for high-end communications applications. Integrated with up to 56 transceivers, it is claimed to offer total bandwidth of up to 364Gbit/s.

The inclusion of transceivers makes the Nextreme-2T a viable choice for high-performance networking applications, such as switches, routers, traffic management, metro transmission and mobile backhaul, the company said.

Like the 90nm lineup, the new products are based on a triple-oxide transistor technology that is said to provide up to 80 percent lower power consumption than FPGAs. EASIC is currently engaged with early-access customers. Mainstream availability will commence in Q4.

- Mark LaPedus
EE Times





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