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Design tool shortens programming of mixed-signal devices

Posted: 01 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:mixed-signal? design tool? automotive?

Lattice Semiconductor has released the PAC-Designer software design tool suite ver 4.99a. The PAC-Designer tool suite supports Lattice's AECQ100-qualified automotive Power Manager II (LA-ispPAC-POWR1014/A) devices. It also provides easy-to-use, point-and-click, intuitive design and verification support for all Power Manager and ispClock mixed signal devices.

Today's automotive designs employ advanced CPUs, FPGAs and ASICs requiring multiple power supplies. The software tools enable designers to work on and fine-tune the power management algorithm used to control and monitor these diverse power supplies. Lattice said the resulting board-specific power management design is more accurate, needs less circuit board area and costs less than traditional designs using multiple off-the-shelf dedicated devices.

Features of design tool
Common power management functions found on circuit boards are hot-swap control, voltage supervision, supply sequencing and reset generation. Ensuring board reliability, all board-mounted power supplies should be sequenced and monitored via a power management algorithm. Generally, the power management algorithm is either changed or fine tuned during the board debug process to achieve unforeseen device power-up behavior. Traditional solutions are hard-wired and cannot be changed without an expensive board respin. Lattice's Windows-based PAC-Designer software enables implementation of a new power management algorithm in Lattice's Power Manager II devices within minutes.

Similarly, clock network designs require timing adjustments during the board debug phase. The Lattice ispClock devices support an in-system programmable skew mechanism. With the PAC-Designer software, designers can precisely alter the clock skew of each of the clock nets. Before, clock skew has been implemented by "snaking" clock traces on the board, and any change to the skew was implemented through a time consuming, expensive board re-spin. Now, using the PAC-Designer software, the clock network skew is altered by reprogramming the ispClock device.

- Clive Maxfield
Programmable Logic DesignLine





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