Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > FPGAs/PLDs
?
?
FPGAs/PLDs??

Custom PCI timing budgets for Spartan-3 Generation FPGAs

Posted: 12 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:PCI timing budgets? Spartan-3 FPGAs? system designers?

The PCI Local Bus Specification, Revision 3.0 (the PCI specification), defines two timing budgets. One timing budget is for use with 33MHz operation, and the other timing budget is for use with 66MHz operation. These two timing budgets define the I/O timing parameters for compliant 33MHz and 66MHz components.

In open systems, compliance with the PCI specification is a requirement to ensure interoperability. However, in embedded designs, it is possible to create custom timing budgets that enable system designers to do one or more of the following:

? Reduce total system cost by using less expensive devices

? Achieve higher data transfer rates than allowed by specification

? Add more loads to the bus to accommodate additional devices and connectors

? Increase the physical length of the bus to accommodate novel bus topologies.

View the PDF document for more information.





Article Comments - Custom PCI timing budgets for Sparta...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top