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FPGAs/PLDs??

J Drive: In-System Programming of IEEE Standard 1532 Devices

Posted: 13 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:J Drive programming? programmable logic devices?

The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an insystem device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx Web site. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (or later) FPGAs.

View the PDF document for more information.





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