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Tensilica, Cadence tip CPF-enabled multimedia designer

Posted: 15 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:low-power? multimedia reference design? Common Power Format?

Tensilica Inc. and Cadence have collaborated to create a Common Power Format (CPF)-enabled low-power reference design for a multimedia subsystem based upon its popular 330HiFi audio processor and 388VDO video engine. Cadence and Tensilica engineers worked together to develop an implementation of the Tensilica multiprocessor audio/video platform using the complete Cadence Low-Power Solution including Encounter RTL Compiler global synthesis, Encounter Conformal Low Power and the SoC Encounter RTL-to-GDSII system.

The 388VDO video engine is a fully programmable codec processor that supports multi-standard, multiresolution video. Both are targeted at mobile handsets and personal media players (PMPs). SoC designers can now build upon the Tensilica reference design by employing the Cadence Low-Power Solution to deliver the lowest possible power for power-sensitive mobile applications.

"The combination of Tensilica IP with the Cadence Low-Power Solution equips customers with all the tools and technology they need to create power-efficient, portable multimedia chips," said Chris Jones, Tensilica's director of strategic alliances. "By using this reference flow based on the widely deployed Common Power Format, our customers will be able to save precious design time while employing the most advanced techniques for low-power design."

For 330HiFi and 388VDO users, Tensilica will deliver example reference scripts for Encounter RTL Compiler global synthesis, Encounter Conformal Low Power and the SoC Encounter RTL-to-GDSII system, along with example CPF files describing power intent for the 388VDO processor. The CPF package will be available in Q4 08.





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