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Mobile data travels quickly over West Bridge

Posted: 16 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:West Bridge? multimedia handset? NAND? processor?

As the integration of handheld devices continues, handset designers are increasingly called upon to consolidate audio, video, Internet and navigation services onto a single device. They must design handsets with greater memory capacity and faster peripheral interfaces to support processing of increasing amounts of multimedia data.

Although processor manufacturing process technology nodes advance roughly every two years, memory technology advances every six months. Thus, handset designers must strike a balance between creating a stable, mature platform and attempting to incorporate next-generation features that require larger memory and faster interfacesall while keeping total size, power and cost within limits.

The world of PCs saw a similar trend in the early 1990s, when the peripherals attached to processors changed more quickly than manufacturers could release new processors. Intel solved the problem by creating the north and south bridges to interface processors to memory and other peripherals. The bridges enabled processor suppliers to address manufacturers' immediate needs while buying time to build next-generation chipsets. The use in mobile handsets of a bridge similar to the ones used in PCsin this case dubbed the West Bridgecan give designers enough flexibility to provide both fast design cycles and reliable, high-speed interfaces to the latest storage and other peripherals.

As memory process technology nodes shrink, error correcting code capabilities in the flash controller must increase to maintain data integrity.

NAND needs
The amount of data that a mobile device's internal memory may transfer is limited, but memory can be added by introducing Secure Digital (SD) or MMC storage to the architecturean attractive option as it introduces very little extra cost. The memory of choice for mobile devices is NAND flash, with its low cost per bit, higher density and small size. NAND controller implementation limits the type of NAND devices that may be used to single-level cell (SLC) and multilevel cell (MLC).

All NAND devices require certain controller-side overhead to maximize device life spans. The controller must understand how many bad blocks exist (bad-block management); some are marked as bad by manufacturers, and others will become unusable over the device's lifetime. To minimize the number of blocks that wear out, the controller can employ wear-leveling techniques that spread writes evenly throughout the storage device. The controller should also manage errors by means of its execution control chart (ECC) state machine. The support level for NAND management changes with the process node.

Most mobile device architectures do not yet take full advantage of the performance and reliability offered by NAND flash, offering a less impressive user experience than could be provided. Furthermore, although densities are increasing, mobile processors are not able to keep up. Mobile architectures must adapt to support changing NAND flash requirements quickly and efficiently if designers are to keep removable and embedded memory flexible while maximizing performance.

Multimedia applications require the ability to handle large amounts of data on both mobile devices and PCs. Sideloading is commonly accomplished directly between the mobile handset and PC across a USB cable. Pictures, videos and games also fall into the same usage model. Becoming truly mobile means being able to transfer data to mobile devices quickly, and having a large amount of memory in the handset onto which to save data.

Deal with its limitations
USB is the choice for communication between handsets and PCs because of its stable, well-defined protocol and high data rate. Although low-speed USB is used largely for human interface devices, full- and high-speed USB are used for data transfers at 12Mbit/s and 480Mbit/s, respectively. Today's mobile processors integrate full-speed USB, but full-speed USB is already insufficient for the large data transfers required for multimedia support.

Designers cannot wait for processor manufacturers to integrate high-speed USB into next-generation devices. Instead, they use a dedicated USB controller to implement those capabilities. Unfortunately, the faster the interface, the greater the burden it places on the main application processor.

One approach for reducing processor load is to add another processor to handle communications with a PC and management of the NAND internal memory. But having a second processor negatively affects price, size and power consumption. Another alternative is pushing users to cellular networks for connectivity and data download. But cellular nets are already congested, and users are reluctant to incur additional costs.

Even as manufacturers race to integrate new memory and peripheral interfaces into mobile processors, new interfaces are on the horizon. But the challenge for designers is that the processors used in mobile systems are slow to integrate and support faster-changing technologies.

Finding the bottleneck
Addressing throughput problems in mobile handsets requires locating the bottlenecks in today's mobile architectures (e.g. a handset has a main processor interfacing to the RF block of the handset and controlling the LCD, keypad, memory, audio and camera, and PC connectivity and other peripherals).

For a data packet to be saved into attached storage memory, the processor must be interrupted. Once the processor is ready, it moves data to the SRAM for buffering and then copies it to the storage device. During this process, the processor might be interrupted multiple times to attend to higher-priority tasks. The processor memory interface may be shared between the USB controller and the storage device. Such an architecture introduces multiple bottlenecks and keeps the processor active for extended periods of time.

If transfer rates are to be improved and power efficiency increased, the processor must be removed from the data path. Moreover, data must travel from the host PC to storage across a direct data path without bus contention. A bridge addresses all those issues and provides the additional horsepower needed without requiring another processor, thus alleviating congestion on the memory bus of the processor, letting the processor work on other tasks and disconnecting the memory tech node from the processor.

This architecture, called the West Bridge, offloads the processor from the data transfer path between PCs and mobile devices, providing users with fast sideloading speeds. It also connects to the latest NAND, SD, MMC and HDD memories; because the cycle time is shorter for bridges than for CPUs, the West Bridge can track these technologies more quickly. Bridges eliminate the main bottlenecks in the path between PCs and internal or external mobile device memory.

The West Bridge creates a direct path from a host PC to mass storage. The processor is interrupted only when needed. Bridges can be adapted quickly to keep up with NAND flash tech advances, supporting MLC with ECC, wear leveling and bad-block management.

- Hussein Osman
Staff Systems Engineer, Data Communication Division
Cypress Semiconductor Corp.





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