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Grasp SystemVerilog testbench debug and analysis

Posted: 16 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:SystemVerilog? SoC debug? verification?

Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many of today"s applications take advantage of this trend. An important point that is often missed is the accompanying growth in verification complexity. Indeed, the verification task for a design that is twice as big is actually more than doubled. The verification team has to deal with a bigger state-space and the application, which is what the verification environment attempts to mimic, gets much "bigger".

Simply building faster tools like simulators will not solve this problem. Rather, it requires capabilities and associated methodologies that make it easier to set up complex verification environmentsenvironments that in the end ensure that the application on the chip works as expected. Fortunately, SystemVerilog provides a compelling advantage in addressing the complexity challenge. It is not simply a new language for describing complex structures, but a platform for enabling advanced methodologies and automation.

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