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Clock generator eases configuration in multiple ICs

Posted: 10 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:clock generator? processor? buffer?

Silicon Laboratories Inc. has created a clock generator known as Si5338, which can synthesize any frequency from 0.16MHz to 350MHz and choose frequencies to 700MHz on each of the device's four differential outputs.

At 1ps rms random jitter typical, the Si5338 can simultaneously generate low jitter clocks for multiple ICs like processors, FPGAs, ASICs, memory and PHY transceivers. The device provides four differential or eight single-ended outputs per device, removing the need for external clock distribution buffers. In addition to frequency, each output clock is independently configurable in terms of supply voltage (1.5V, 1.8V, 2.5V, 3.3V) and signal format (LVPECL, LVDS, CMOS, HCSL, SSTL, HSTL).

The Si5338's any-rate, any-output capability eases timing designs by substituting fixed frequency clock generators, discrete level translators and crystal oscillators with a single device, minimizing cost and real estate and lowering power by 50 percent compared to traditional products, according to the company. To simplify board-level test, the Si5338 has a frequency margining feature that enables the frequency of each output clock to be varied dynamically over the 0.16MHz to 350MHz range, eliminating discrete XOs and making it easier for hardware designers to have consistent, reliable system operation over temperature and voltage.

- Ismini Scouras
eeProductCenter





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