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Intel, AMD compete in 45nm leadership

Posted: 17 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:45nm processor?

Advanced Micro Devices Inc. (AMD) has officially launched Shanghai, its first 45nm processor server just days earlier than Intel's formal disclosure of its first 45nm server chips. The quest for dominance in high-end PC processors comes as analysts predict a drop in the overall CPU market in 2009.

The four-core Shanghai proves AMD has a robust 45nm process and gives it an edge for as much as a year in servers backing four or more chips. However, Intel will gain a significant advantage with its Nehalem server processors coming late next year that support up to eight dual-threaded cores for similar high-end systems.

Shanghai is essentially a 45nm shrink of AMD's delayed quad-core Barcelona design. By contrast, Nehalem chips integrate a memory controller and Intel's new high-speed Quick Path Interconnect, similar to the design of AMD's Opteron CPUs.

"Nehalem is a big leap forward for Intel compared to Shanghai, which is a somewhat improved shrink of AMD's previous chip," said Nathan Brookwood, principal of market watchers Insight64.

Promoting usability
A panel of high-end system integrators said with the Shanghai debut they expect to see rising use of AMD processors. But they predicted the server chip market will continue to be a heated one with Intel and AMD trading off leadership in different sectors over time.

Brookwood said he believes AMD's server market share will trend up slightly in the short-term with Shanghai. However, Ben Reitzes of Barclays Capital projects AMD's market share in PC processors overall will steadily decline from 22.2 percent last year to 17.9 percent in 2010, mainly because of Intel's growth in mobile CPUs with its Atom chip.

Reitzes is one of the several analysts that expect a slowdown in the overall PC market. He projected PC processor sales could drop 6 percent in 2009 because of the souring economic climate. He added that the server CPU market will be flat next year.

Craig Berger, analyst with FBR Research, cut his estimates for PC sales as well as Intel's and AMD's earnings in the current quarter.

AMD's Shanghai adds about 400MHz to Barcelona's data rates, with about 2.7GHz. That's below the 3+GHz for Intel's Nehalem parts, however AMD has long argued its chips crunch through more work per MHz than its rivals.

Power usage
The initial Shanghai chips dissipate a maximum 75W at 2.3GHz. Less and more powerful versions will follow using 55W and 105W max. It comes in at prices ranging from $2,149 to $377 in thousand unit quantities.

The chip doubles to 8Mbytes the earlier amount of cache memory, 6Mbytes of it at L3. Support for external DDR2 chips is raised from 667MHz to 800MHz.

Overall performance for Shanghai is about 20 to 25 percent higher than Barcelona, making its biggest gains in Java server benchmarks heavily influenced by the added cache. Some stepwise improvements in power management, caching and virtualization support also boost performance.

AMD conducted a range of benchmarks showing the chip slightly to significantly ahead of Intel's Harpertown, a 65nm server chip. It also meets or beat Intel's Dunnington, a six-core 65nm CPU.

But Intel should leapfrog Shanghai with its Nehalem family, thanks partly to its use of integrated memory controllers, a high-speed CPU bus and support for two threads per core. Unlike AMD, Intel's 45nm process backs high-k metal gates, which are expected to lower circuit power leakage and add performance.

Intel's next chips
Intel is expected to release server chips initially for systems with one socket, then versions for systems with two sockets early in 2009. Chips for high-end systems supporting four to eight sockets will come late next year, but some will have up to eight cores.

AMD will counterattack in late 2009 with Istanbul, a native six-core design. It will be followed by Sao Paolo, a chip using two Istanbul dice in a multichip module debuting in 2010.

Unlike Shanghai, which fits into existing Barcelona systems, Istanbul and Sao Paolo will need new chipsets. AMD will launch its own server chipset in 2009 for its Fiorano platform, its first to support 5GHz PCIe.

The Maranello platform for Sao Paolo in 2010 will be AMD's first to support DDR3 memory. It will also sport direct links to the processor to support user management software that can control CPU clocking and utilization.

AMD's new approach
Eventually, AMD sees PCIe links and security accelerators getting integrated into its server chips, said Patrick Patla, general manager, server group, AMD. Sun Microsystems Inc. has integrated Express, security and even Ethernet controllers into its Niagara server CPUs.

"You can never choose the right PHY version of Ethernet for all your customers, so it would be better to integrate some form of PCIe instead," he added.

Shanghai represents shifts in both design and process technology for AMD. It marks the company's first use of immersion lithography, a costly step Intel said it was able to put off until the 32nm node. AMD officials counter using dry immersion forces Intel to use double-patterning lithography that can lower yields.

"There are advantages and disadvantages to both processes," said Don Scansen, technology analyst with Semiconductor Insights, who has been examining a Shanghai chip.

"AMD has been able to squeeze a lot out of polysilicon using IBM's process and strained silicon engineering," he added. "They have increased drive current about 25 percent and cut leakage way down," he noted.

"Shanghai shows good use of smaller features to get strained silicon and embedded silicon germanium elements from the IBM process technology working closer to the channel where it's needed to be able to hit the benchmarks they wanted," Scansen said.

But Intel's Nehalem chips may be able to use the high-k metal gate materials in its process to boost transistor drive current as much as 40 percent, he added.

Intel will continue its lead in process technology, expecting to deliver its first products using a 32nm process before the end of 2009. AMD will probably follow sometime in 2010, said the Barclays analyst.

AMD also changed its design and test methodology starting with Shanghai.

In January, it named Raghuram Tupuri as the engineering manager in charge of all chip and platform validation for the product, after Barcelona delays caused by a bug which escaped its testers. It also adopted new analysis tools and struck closer partnerships with OEMs who helped test the chip earlier in the process.

"We jumped into a very deep relationship with some of our OEMs in co-validation," Tupuri said.

AMD also adopted a SoC design methodology starting with Shanghai.

"We have moved away from a monolithic design done at one location to centers of excellence, each responsible for a particular set of silicon blocks or overall SoC integration," said Jeff VerHeul, VP, central engineering, AMD. "We think we are months shorter in time-to-tapeout with this method," he added.

"The company has defined a set of silicon interface standards for internal use in hooking up the various logic and memory blocks. The interfaces will not be publicly released, because AMD currently does not expect to use silicon blocks from outside the company," he noted.

Other developments
Intel also is rolling out a new SoC methodology for its CPU designs. Both companies are expected to roll out notebook chips that merge x86 and graphics cores in 2009.

"AMD's design engineers have seen no adverse impacts from the move to split off AMD's fab operations into a foundry separate from the rest of the company," said VerHeul.

"We still have the same people working with the same folks, and we still retain the test and packaging business," said Patla.

- Rick Merritt
EE Times





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