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aBCD process tech cuts voltage transistor pitch

Posted: 26 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:foundry? aBCD process? advanced bipolar CMOS-DMOS node?

MagnaChip Semiconductor Ltd has announced the availability of its 0.18?m and 0.35?m advanced bipolar CMOS-DMOS (aBCD) process technologies for foundry customers.

The aBCD process technologies represent the latest solutions of Application Specific Technology to meet the specialized customer needs for specific applications. The flexibility of two aBCD process nodes, 0.18?m and 0.35?m, allow our customers to address a wide range of applications.

The 0.18?m aBCD process is suitable for complex, highly integrated power management ICs, such as those found in mobile handsets. The 0.35?m aBCD, with higher voltage and power capabilities, is designed for applications such as LED driver IC, for LCD TVs and notebooks. MagnaChip has combined the cost and device performance of smaller chips with better leakage characteristics, more uniform and higher isolation breakdown voltage and improved latch-up immunity. First products from the new aBCD processes are sampling now. Mass production will begin in the 1H 09.

Namkyu Park, VP of technology engineering of MagnaChip's semiconductor manufacturing services, commented, "MagnaChip's aBCD process technology has adopted a DTI (Deep Trench Isolation) process, rather than the conventional junction isolation process in order to satisfy reliability and cost requirements. Within the aBCD process, the DMOS device was optimized for low Rsp (Specific Ron), enabling improved drive capability for power management ICs. With these features, we have designed a robust application-specific technology for foundry customers, a departure from traditional offerings."

With DTI technology, the MagnaChip aBCD process achieves cost reduction by dramatically reducing the high voltage transistor pitch, up to almost half when compared to normal junction isolation. Better product reliability and latch-up characteristics are achieved by locating the deep trench isolation between high voltage junctions prone to latch-up, eliminating one of the biggest concerns in power management IC design. In addition, the process provides better device performance, such as high switching speed, by removing parasitic resistance and capacitance between high voltage wells. It also offers much lower leakage characteristics and as more repeatable and higher breakdown voltage characteristics than junction isolation.

Both technology nodes are fully voltage scalable enabling designers to apply EDMOS or LDMOS devices at various voltage levels. Additionally, MagnaChip offers process options such as N/P-EDMOS, N/P-LDMOS, low voltage and high voltage BJT, 1~4fF MIM Capacitor, 0.2k~10k ohm resistor, Schottky diode, Zener diode, low voltage and high voltage diode, one-time programmable memory, EEPROM, SRAM, and native CMOS. MagnaChip also provides a quality designer friendly process design kit.





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