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Surpass LTE requirements, goals

Posted: 01 Dec 2008 ?? ?Print Version ?Bookmark and Share

Keywords:LTE? IP network? OFDM? 4G?

Long Term Evolution (LTE), one of the wireless industry's 4G solutions rolling out over the next several years, presents a series of lofty goals. These goals create a difficult set of challenges for technology providers, equipment manufacturers and service providers.

LTE is the next-generation of the 3G UMTS wireless protocol. It is being developed by the Third Generation Partnership Project (3GPP) with the aim of moving cellular toward a packet-based all-IP network. Among the goals of LTE are significantly higher download and upload data rates (100Mbit/s and 50Mbit/s, respectively), and packet latencies no more than 5ms. The latter is increasingly critical for new services such as wireless VoIP. For good measure, the technology must also offer greater spectrum efficiency, increased capacity and reduced cost-per-bit-communicated.

LTE reaches these goals by using several concepts that add significantly to the complexity of the technology. These include more complex modulation schemes in the download and upload directions, flexible channel bandwidths and a MIMO architecture, which in some cases requires multiple antennas. Ultimately, the increased complexity in LTE will require very powerful, flexible and innovative processing in base stations and handsets.

LTE implements the OFDM modulation scheme in the downlink direction and an OFDM-derivative, single-carrier frequency division multiple access (SC-FDMA), in the uplink. SC-FDMA is used for uplink because it offers greater power amplifier efficiency than OFDM, which translates into longer battery life for handsets. OFDM is rather complex, incorporating 2,048 sub-carriers with a 15kHz spacing. This high number of sub-carriers enhances OFDM's multi-path capabilities, which strengthens its resistance to interference, improves spectral efficiencies and increases data rates.

Scalable bandwidths that scale from 1.25MHz to 20MHz in both the downlink and uplink directions allow LTE to use both new and existing frequency bands. A MIMO architecture helps LTE achieve its high data rates through multiple signal paths. But here again, LTE implements slightly different schemes for downloads and uploads in order to control costs in LTE handsets. MIMO has the potential to increase data rates beyond 100/50Mbit/s if handsets are equipped with multiple antennas.

To address the high level of complexity in LTE, TI has developed the TCI6487 multicore DSP with embedded accelerators for 2G, 3G and 4G wireless base station standards that are used in baseband processing. It has three C64 + DSP cores and provides 3GHz of DSP processing power with which to tackle LTE baseband tasks such as MAC and PHY processing.

SRIO supports a variety of peer-to-peer configurations, including a U-shaped daisy chain.

Co-processing accelerators
To achieve LTE's higher data rates and ensure packet latencies of less than 5ms, the device includes a Viterbi and a Turbo Co-Processor (TCP) to offload the coding/decoding burden from the main DSP cores. These co-processing accelerators handle much of the mathematically intense coding functions needed in LTE processing. Specifically, the TCP2 was developed as a flexible accelerator to support Turbo decoding; it can support LTE and all 3GPP family of standards. Offloading the Turbo decoding from the TCI6487's DSP cores frees up processing capacity for MAC and PHY processing. Or, alternately, the available processing headroom can be deployed to process more users in base stations in particularly dense cells.

A certain level of flexibility and re-configurability is critical if a base station is to meet the higher requirements of LTE. For example, in a low density cell, the DSP could be deployed as a one-chip solution with one core dedicated to MAC processing and the other two performing PHY level transmit and receive functions. High-density cells with many users taking advantage of LTE's higher data rates present a different set of challenges. In this case, multiple DSPs might be deployed with one chip performing all of the cell's MAC processing and the other devices handling PHY transmit and receive tasks. In this way, DSPs could be dedicated to either the OFDM or the SC-FDMA modulation schemes implemented in the LTE download and upload modes.

A multi-level on-chip memory architecture is required to capitalize on the flexibility inherent in a multicore device. With the TCI6487, level 1 (L1) memory can be configured as either cache or standard memory storage. In addition, the amount of L2 memory devoted to each core is partially scalable. The total of 3Mbytes of L2 memory can be split evenly between the three cores, or the three cores could be assigned 0.5-, 1- and 1.5Mbyte each. This can affect the efficiency of a complex LTE deployment where several distinct processing needs are ongoing at the same time. For example, a core that is processing a memory-intense task might be configured with 1.5Mbyte of L2 memory.

Keeping up with LTE
To avoid bottlenecks, transferring data through a base station at LTE rates requires very high-speed I/O for moving data into and out of the DSPs. As a result, the peripherals on the TCI6487 include the serial rapid I/O (SRIO) interface. SRIO extends the flexibility and scalability of the device to the board level, lowering board complexities and costs.

The two-lane SRIO interface is capable of data rates of 1.25-, 2.5- or 3.125Gbit/s on each lane. It is configured as a two single-lane high-speed dedicated links between devices such as ASICs or FPGAs on the circuit board or among boards in an LTE base station backplane.

In another configuration, SRIO could interconnect multiple DSPs in a peer-to-peer arrangement or in a master/slave architecture. When configured as on-board peer-to-peer connections between chips, the dedicated SRIO lanes can eliminate the bottleneck problems that shared buses run into when they become overloaded. With the huge amount of data that LTE is capable of transferring, this can become very critical. The scalability and flexibility of the SRIO interface enables a wide variety of architectures, including star, ring, U-shaped daisy chain and others.

Another option for chip-to-chip interconnects on LTE base station cards is a GbE switch fabric. To enable this, the TCI6487 also incorporates a GbE interface.

Basic 3G or 3.5G antenna architecture is shown.

Antenna interface
Unlike the slower 3G and 3.5G protocols where DSPs could be interfaced to antenna data streams via the external memory interface on an ASIC or FPGA, the higher transfer speeds and lower packet latency requirements of the 4G LTE specification require next-generation antenna solutions. Fortunately, at least two industry standard antenna interfaces, the Common Public Radio Interface (CPRI) and the Open Base Station Architecture Initiative (OBSAI) interface, meet LTE's need for speed. CPRI's link rates begin at 614.4Mbit/s and go up to 2.4Gbit/s. OBSAI supports rates ranging from 768Mbit/s to 3.07Gbit/s. Because of the high data rates of CPRI and OBSAI, LTE antenna data streams can be routed directly to the baseband processor, eliminating the ASIC or FPGA that typically interfaces antenna data to the DSP.

The TCI6487 chip features a six-lane antenna interface and supports both the CPRI and OBSAI standards. In addition, the six-lane OBSAI/CPRI antenna interface can be used to configure a number of architectures on a board, same as the SRIO interface. Each of the antenna interface links can support either uplink or downlink modes with as many as 48 uplink and 24 downlink data streams.

Software cuts time-to-market
Infrastructure OEMs are developing multi-standard, flexible baseband cards using a farm of TCI6487 devices. Such a platform allows for flexible implementation, which is important for initial LTE platforms that are used in labs or field trials. Infrastructure vendors prefer to develop multi-standard platforms since using a single hardware platform for multiple standards reduces R&D investment and quickens time-to-market. Some infrastructure vendors are developing platforms that are capable of supporting W-CDMA-HSPA and LTE, while others are developing platforms that are capable of supporting WiMAX and LTE.

A library of ready-to-implement and fully-tested LTE software modules support the TCI6487 DSP and shorten a new base station's time-to-market. All of the LTE PHY functions, including modulation mapping, scrambling, channel equalization, RACH processing and others, have been productized and made available as library modules.

New CPRI- or OBSAI-based antenna architectures allows for direct connectivity to the backplane.

Moreover, compatibility with TI's previous generations of wireless infrastructure DSPs means that many of the common functions in 3G and 3.5G W-CDMA protocols can be migrated seamlessly to LTE applications. And the software development tools used on previous generations of TI DSPs such as Code Composer Studio are also available on the TCI6487 chip, offering developers a familiar and efficient set of software development tools.

Programming the TCI6487 has been simplified with the addition of a Linux-based development environment that is available from a TI third-party supplier, Virtual Logix Inc. Running alongside the DSP/BIOS, the Virtual Logix Linux kernel offers an effective environment to quickly develop MAC and PHY programming algorithms as well as other software modules for LTE. Hardware development platforms, such as CommAgility Ltd's AMC-6487 platform featuring three TCI6487s, are also available to facilitate rapid development.

Lowering power use
Power consumption is always a concern in wireless base stations. Higher power consumption drives up operating costs for service providers. LTE's requirements of reduced cost-per-bit-communicated cannot be met without addressing the power consumption of base stations.

Because it's a multicore DSP, the TCI6487 chip can reduce power consumption significantly over implementations of discrete DSPs, each with its own set of peripheral interfaces. By consolidating the number of I/O interfaces onto one chip with three DSP cores, a multicore DSP can reduce the power consumed by the peripheral interfaces since they are shared by more than one DSP core.

In addition, TI's SmartReflex power-reducing technology has also been implemented in the TCI6487. Besides traditional power-saving methods such as power switching, isolation and voltage shifting which facilitate a granular approach to partitioning a device's power domains, SmartReflex technology allows designers to decrease both static and dynamic power consumption while meeting performance requirements of LTE. Smart Reflex technology considers factors such as device-specific silicon characteristics based on the manufacturing process as well as thermal parameters. This effectively reduces power within the DSP while maintaining performance targets of 1GHz for the TCI6487. Depending upon the algorithm used, this allows the TCI6487 to be an extremely power-efficient DSP that limits power consumption to just 6W. This low power characteristic allows for the use of six to eight devices on a single card without breaking the power budget. This configuration supports one of the key goals of the infrastructure vendors, that is, to support three sectors or cells of LTE baseband processing on a single hardware card.

The high data rates of LTE and other 4G wireless solutions will certainly open the door to a host of new wireless applications and services. Meeting and exceeding the high performance requirements and increased complexity of LTE systems is no mean feat either, but technology suppliers like TI are well on their way to enabling this powerful next-generation wireless infrastructure.

- Manish Patel
Product Manager
Communications Infrastructure Business Unit, DSP Systems
Texas Instruments Inc.





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